diff --git a/.gitignore b/.gitignore index a056d82f8..8e9c77346 100644 --- a/.gitignore +++ b/.gitignore @@ -117,10 +117,10 @@ tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag sim/branch_BP_GSHARE10.log sim/branch_BP_GSHARE16.log -sim/imperas.log +sim/questa/imperas.log sim/results-error/ sim/test1.rep -sim/vsim.log +sim/questa/vsim.log tests/coverage/*.elf *.elf.memfile sim/*Cache.log @@ -211,3 +211,13 @@ sim/vcs/simprofile_dir sim/vcs/ucli.key sim/vcs/verdi_config_file sim/*/testbench.vcd +sim/questa/imperas.log +sim/questa/regression.log +sim/questa/regression_logs/* +sim/questa/regression_ucdbs/* +sim/questa/riscv.ucdb +sim/questa/riscv.ucdb.log +sim/questa/riscv.ucdb.summary.log +sim/questa/riscv.ucdb.testdetails.log +tests/riscvdv + diff --git a/Makefile b/Makefile index c96a2e2c6..a16530672 100644 --- a/Makefile +++ b/Makefile @@ -2,6 +2,8 @@ # Top-level Makefile for CORE-V-Wally # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +SIM = ${WALLY}/sim + all: make install make riscof @@ -31,8 +33,8 @@ testfloat: cd ${WALLY}/tests/fp; ./create_all_vectors.sh verify: - cd ${WALLY}/sim; ./regression-wally - cd ${WALLY}/sim; ./sim-testfloat-batch all + cd ${SIM}; ./regression-wally + cd ${SIM}/sim; ./sim-testfloat-batch all make imperasdv imperasdv: @@ -40,13 +42,13 @@ imperasdv: iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m imperasdv_cov: - touch ${WALLY}/sim/seed0.txt - echo "0" > ${WALLY}/sim/seed0.txt + touch ${SIM}/seed0.txt + echo "0" > ${SIM}/seed0.txt # /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --verbose --seed 0 --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m -# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb ${WALLY}/sim/cov/rv64gc_arch64i.ucdb --verbose -# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb riscv.ucdb --verbose - run-elf-cov.bash --elf ${WALLY}/tests/output_folder/asm_test/riscv_arithmetic_basic_test_0.elf --seed ${WALLY}/sim/seed0.txt --coverdb riscv.ucdb --verbose - vcover report -details -html sim/riscv.ucdb +# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/cov/rv64gc_arch64i.ucdb --verbose +# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose + run-elf-cov.bash --elf ${WALLY}/tests/riscvdv/asm_test/riscv_arithmetic_basic_test_0.elf --seed ${SIM}/questa/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose + vcover report -details -html ${SIM}/questa/riscv.ucdb funcovreg: #iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m --cover @@ -55,58 +57,58 @@ funcovreg: #iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/Q --cover rm -f ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/*/src/*/dut/my.elf iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I --cover - vcover report -details -html sim/riscv.ucdb + vcover report -details -html ${SIM}/questa/riscv.ucdb # test_name=riscv_arithmetic_basic_test rvdv: - python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen >> sim/regression_logs/${test_name}.log 2>&1 - python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile >> sim/regression_logs/${test_name}.log 2>&1 - python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim >> sim/regression_logs/${test_name}.log 2>&1 -# run-elf.bash --seed ${WALLY}/sim/seed0.txt --verbose --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o >> sim/regression_logs/${test_name}.log 2>&1 - run-elf-cov.bash --seed ${WALLY}/sim/seed0.txt --verbose --coverdb sim/riscv.ucdb --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o >> sim/regression_logs/${test_name}.log 2>&1 - cp sim/riscv.ucdb sim/regression_ucdbs/${test_name}.ucdb + python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1 + python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1 + python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1 +# run-elf.bash --seed ${SIM}/questa/seed0.txt --verbose --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1 + run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/riscv.ucdb --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1 + cp ${SIM}/questa/riscv.ucdb ${SIM}/questa/regression_ucdbs/${test_name}.ucdb rvdv_regression: - mkdir -p sim/regression_logs - mkdir -p sim/regression_ucdbs - cd sim/regression_logs && rm -rf * - cd sim/regression_ucdbs && rm -rf * - make rvdv test_name=riscv_arithmetic_basic_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_amo_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_ebreak_debug_mode_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_ebreak_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_floating_point_arithmetic_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_floating_point_mmu_stress_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_floating_point_rand_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_full_interrupt_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_hint_instr_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_illegal_instr_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_invalid_csr_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_jump_stress_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_loop_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_machine_mode_rand_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_mmu_stress_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_no_fence_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_non_compressed_instr_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_pmp_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_privileged_mode_rand_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_rand_instr_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_rand_jump_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_sfence_exception_test >> sim/regression.log 2>&1 - make rvdv test_name=riscv_unaligned_load_store_test >> sim/regression.log 2>&1 + mkdir -p ${SIM}/questa/regression_logs + mkdir -p ${SIM}/questa/regression_ucdbs + cd ${SIM}/questa/regression_logs && rm -rf * + cd ${SIM}/questa/regression_ucdbs && rm -rf * + make rvdv test_name=riscv_arithmetic_basic_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_amo_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_ebreak_debug_mode_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_ebreak_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_floating_point_arithmetic_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_floating_point_mmu_stress_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_floating_point_rand_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_full_interrupt_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_hint_instr_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_illegal_instr_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_invalid_csr_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_jump_stress_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_loop_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_machine_mode_rand_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_mmu_stress_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_no_fence_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_non_compressed_instr_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_pmp_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_privileged_mode_rand_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_rand_instr_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_rand_jump_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_sfence_exception_test >> ${SIM}/questa/regression.log 2>&1 + make rvdv test_name=riscv_unaligned_load_store_test >> ${SIM}/questa/regression.log 2>&1 rvdv_combine_coverage: - mkdir -p sim/regcov - cd sim/regcov && rm -rf * - vcover merge sim/regcov/regcov.ucdb sim/regression_ucdbs/* -suppress 6854 -64 - vcover report -details -html sim/regcov/regcov.ucdb - vcover report sim/regcov/regcov.ucdb -details -cvg > sim/regcov/regcov.ucdb.log - vcover report sim/regcov/regcov.ucdb -testdetails -cvg > sim/regcov/regcov.ucdb.testdetails.log - vcover report sim/regcov/regcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > sim/regcov/regcov.ucdb.summary.log - grep "Total Coverage By Instance" sim/regcov/regcov.ucdb.log + mkdir -p ${SIM}/questa/regcov + cd ${SIM}/questa/regcov && rm -rf * + vcover merge ${SIM}/questa/regcov/regcov.ucdb ${SIM}/questa/regression_ucdbs/* -suppress 6854 -64 + vcover report -details -html ${SIM}/questa/regcov/regcov.ucdb + vcover report ${SIM}/questa/regcov/regcov.ucdb -details -cvg > ${SIM}/questa/regcov/regcov.ucdb.log + vcover report ${SIM}/questa/regcov/regcov.ucdb -testdetails -cvg > ${SIM}/questa/regcov/regcov.ucdb.testdetails.log + vcover report ${SIM}/questa/regcov/regcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > ${SIM}/questa/regcov/regcov.ucdb.summary.log + grep "Total Coverage By Instance" ${SIM}/questa/regcov/regcov.ucdb.log remove_rvdv_artifacts: - rm sim/riscv.ucdb sim/regression.log covhtmlreport/ sim/regression_logs/ sim/regression_ucdbs/ sim/regcov/ -rf + rm ${SIM}/questa/riscv.ucdb ${SIM}/questa/regression.log covhtmlreport/ ${SIM}/questa/regression_logs/ ${SIM}/questa/regression_ucdbs/ ${SIM}/questa/regcov/ -rf collect_riscvdv_regression_coverage: remove_rvdv_artifacts rvdv_regression rvdv_combine_coverage coverage: diff --git a/sim/questa/wally-imperas-cov.do b/sim/questa/wally-imperas-cov.do index 16e908558..4ddd3c229 100644 --- a/sim/questa/wally-imperas-cov.do +++ b/sim/questa/wally-imperas-cov.do @@ -24,8 +24,9 @@ vlib work # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. -vlog +incdir+../config/$1 \ - +incdir+../config/shared \ +vlog +incdir+$env(WALLY)/config/$1 \ + +incdir+$env(WALLY)/config/deriv/$1 \ + +incdir+$env(WALLY)/config/shared \ +define+USE_IMPERAS_DV \ +define+IDV_INCLUDE_TRACE2COV \ +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \ @@ -49,11 +50,11 @@ vlog +incdir+../config/$1 \ +incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \ $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \ \ - ../src/cvw.sv \ - ../testbench/testbench-imperas.sv \ - ../testbench/common/*.sv \ - ../src/*/*.sv \ - ../src/*/*/*.sv \ + $env(WALLY)/src/cvw.sv \ + $env(WALLY)/testbench/testbench-imperas.sv \ + $env(WALLY)/testbench/common/*.sv \ + $env(WALLY)/src/*/*.sv \ + $env(WALLY)/src/*/*/*.sv \ -suppress 2583 \ -suppress 7063 \ +acc @@ -62,7 +63,7 @@ eval vsim workopt +nowarn3829 -fatal 7 \ -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \ +testDir=$env(TESTDIR) $env(OTHERFLAGS) +TRACE2COV_ENABLE=1 -coverage save -onexit ./riscv.ucdb +coverage save -onexit $env(WALLY)/sim/questa/riscv.ucdb view wave @@ -72,7 +73,7 @@ view wave run -all -noview ../testbench/testbench-imperas.sv +noview $env(WALLY)/testbench/testbench-imperas.sv view wave quit -f