diff --git a/wally-pipelined/src/mmu/tlbcontrol.sv b/wally-pipelined/src/mmu/tlbcontrol.sv
index c161ad2f2..cd938625b 100644
--- a/wally-pipelined/src/mmu/tlbcontrol.sv
+++ b/wally-pipelined/src/mmu/tlbcontrol.sv
@@ -122,5 +122,5 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
   endgenerate
 
   assign TLBHit = CAMHit & TLBAccess;
-  assign TLBMiss = ~TLBHit & ~TLBFlush & Translate & TLBAccess;
+  assign TLBMiss = ~CAMHit & ~TLBFlush & Translate & TLBAccess;
 endmodule
diff --git a/wally-pipelined/src/privileged/csrs.sv b/wally-pipelined/src/privileged/csrs.sv
index 0daaf4f5e..116f67922 100644
--- a/wally-pipelined/src/privileged/csrs.sv
+++ b/wally-pipelined/src/privileged/csrs.sv
@@ -93,7 +93,7 @@ module csrs #(parameter
       if (`MEM_VIRTMEM)
         flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
       else
-        assign SATP_REGW = 0;
+        assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported
       if (`BUSYBEAR == 1)
         flopenl #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, SCOUNTEREN_REGW);
       else if (`BUILDROOT == 1)