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Fixed syntax errors in arty7 top level.

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This commit is contained in:
Ross Thompson 2023-04-10 16:08:40 -05:00
parent 0700202001
commit 5bcb0f6ace
3 changed files with 8 additions and 3 deletions
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0
fpga/constraints/constraints-artyA7.xdc → fpga/constraints/constraints-ArtyA7.xdc
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5
fpga/generator/wally.tcl
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@ -33,8 +33,13 @@ read_verilog -sv [glob -type f ../src/sdc/*.sv]
set_property include_dirs {../../config/fpga ../../config/shared} [current_fileset] set_property include_dirs {../../config/fpga ../../config/shared} [current_fileset]
if {$board=="ArtyA7"} {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc]
} else {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc] set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc]
}
# define top level # define top level
set_property top fpgaTop [current_fileset] set_property top fpgaTop [current_fileset]

2
fpga/src/fpgaTopArtyA7.v
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@ -405,7 +405,7 @@ module fpgaTop
.ui_clk_sync_rst(ui_clk_sync_rst), .ui_clk_sync_rst(ui_clk_sync_rst),
.aresetn(~reset), .aresetn(~reset),
.sys_rst(reset), .sys_rst(reset),
.mmcm_locked(mmcm_locked); .mmcm_locked(mmcm_locked),
// *** What are these? // *** What are these?
.app_sr_req(1'b0), .app_sr_req(1'b0),