From 5bcb0f6ace8a7737519e75c14f4733b8777287a0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 10 Apr 2023 16:08:40 -0500 Subject: [PATCH] Fixed syntax errors in arty7 top level. --- .../{constraints-artyA7.xdc => constraints-ArtyA7.xdc} | 0 fpga/generator/wally.tcl | 9 +++++++-- fpga/src/fpgaTopArtyA7.v | 2 +- 3 files changed, 8 insertions(+), 3 deletions(-) rename fpga/constraints/{constraints-artyA7.xdc => constraints-ArtyA7.xdc} (100%) diff --git a/fpga/constraints/constraints-artyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc similarity index 100% rename from fpga/constraints/constraints-artyA7.xdc rename to fpga/constraints/constraints-ArtyA7.xdc diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index d435f22b5..8d222e071 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -33,8 +33,13 @@ read_verilog -sv [glob -type f ../src/sdc/*.sv] set_property include_dirs {../../config/fpga ../../config/shared} [current_fileset] -add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc -set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc] +if {$board=="ArtyA7"} { + add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc + set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc] +} else { + add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc + set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc] +} # define top level set_property top fpgaTop [current_fileset] diff --git a/fpga/src/fpgaTopArtyA7.v b/fpga/src/fpgaTopArtyA7.v index 605d8c687..da7ad450e 100644 --- a/fpga/src/fpgaTopArtyA7.v +++ b/fpga/src/fpgaTopArtyA7.v @@ -405,7 +405,7 @@ module fpgaTop .ui_clk_sync_rst(ui_clk_sync_rst), .aresetn(~reset), .sys_rst(reset), - .mmcm_locked(mmcm_locked); + .mmcm_locked(mmcm_locked), // *** What are these? .app_sr_req(1'b0),