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DM accesses to DPC address point to PCM

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Matthew 2024-06-09 15:42:21 -05:00
parent 2fc214bb2d
commit 5ba6e4da0f
2 changed files with 2 additions and 0 deletions
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1
config/shared/debug.vh
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@ -151,6 +151,7 @@
// wallypipelinedcore // wallypipelinedcore
`define TRAPM_REGNO 16'hC000 // 1'b P.ZICSR_SUPPORTED (Read Only) `define TRAPM_REGNO 16'hC000 // 1'b P.ZICSR_SUPPORTED (Read Only)
// src/ifu // src/ifu
`define DPC_REGNO 16'h07B1 // BOZO: Alias to PCM until DPC CSR is added
`define PCM_REGNO 16'hC001 // XLEN P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED `define PCM_REGNO 16'hC001 // XLEN P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED
`define INSTRM_REGNO 16'hC002 // 32'b P.ZICSR_SUPPORTED | P.A_SUPPORTED `define INSTRM_REGNO 16'hC002 // 32'b P.ZICSR_SUPPORTED | P.A_SUPPORTED
// ieu/controller // ieu/controller

1
src/debug/rad.sv
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@ -101,6 +101,7 @@ module rad import cvw::*; #(parameter cvw_t P) (
InvalidRegNo = ~P.ZICSR_SUPPORTED; InvalidRegNo = ~P.ZICSR_SUPPORTED;
RegReadOnly = 1; RegReadOnly = 1;
end end
`DPC_REGNO, // BOZO: Alias to PCM until DPC CSR is added
`PCM_REGNO : begin `PCM_REGNO : begin
ShiftCount = SCANCHAINLEN - PCM_IDX; ShiftCount = SCANCHAINLEN - PCM_IDX;
InvalidRegNo = ~(P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED); InvalidRegNo = ~(P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED);