diff --git a/config/shared/debug.vh b/config/shared/debug.vh
index 034d69993..dce9dbc5b 100755
--- a/config/shared/debug.vh
+++ b/config/shared/debug.vh
@@ -151,6 +151,7 @@
 // wallypipelinedcore
 `define TRAPM_REGNO       16'hC000 // 1'b  P.ZICSR_SUPPORTED (Read Only)
 // src/ifu
+`define DPC_REGNO         16'h07B1 // BOZO: Alias to PCM until DPC CSR is added
 `define PCM_REGNO         16'hC001 // XLEN P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED
 `define INSTRM_REGNO      16'hC002 // 32'b P.ZICSR_SUPPORTED | P.A_SUPPORTED
 // ieu/controller
diff --git a/src/debug/rad.sv b/src/debug/rad.sv
index cceed8a6a..b572c2ca9 100644
--- a/src/debug/rad.sv
+++ b/src/debug/rad.sv
@@ -101,6 +101,7 @@ module rad import cvw::*; #(parameter cvw_t P) (
         InvalidRegNo = ~P.ZICSR_SUPPORTED;
         RegReadOnly = 1;
       end
+      `DPC_REGNO,  // BOZO: Alias to PCM until DPC CSR is added
       `PCM_REGNO : begin
         ShiftCount = SCANCHAINLEN - PCM_IDX;
         InvalidRegNo = ~(P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED);