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update two files tha thad repeated lines in them

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James Stine 2024-06-04 09:25:41 -05:00
parent 2e0c286017
commit 5b50fcd4f4
2 changed files with 0 additions and 4 deletions
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2
src/privileged/csr.sv
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@ -242,8 +242,6 @@ module csr import cvw::*; #(parameter cvw_t P) (
.MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM, .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM, .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM,
.MENVCFG_REGW, .DebugCapture, .DebugScanEn, .DebugScanIn, .DebugScanOut); .MENVCFG_REGW, .DebugCapture, .DebugScanEn, .DebugScanIn, .DebugScanOut);
.MENVCFG_REGW, .DebugCapture, .DebugScanEn, .DebugScanIn, .DebugScanOut);
if (P.S_SUPPORTED) begin:csrs if (P.S_SUPPORTED) begin:csrs
logic STCE; logic STCE;

2
src/privileged/privileged.sv
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@ -154,8 +154,6 @@ module privileged import cvw::*; #(parameter cvw_t P) (
.EPCM, .TrapVectorM, .EPCM, .TrapVectorM,
.CSRReadValW, .IllegalCSRAccessM, .BigEndianM, .CSRReadValW, .IllegalCSRAccessM, .BigEndianM,
.DebugCapture, .DebugScanEn, .DebugScanIn, .DebugScanOut); .DebugCapture, .DebugScanEn, .DebugScanIn, .DebugScanOut);
.CSRReadValW, .IllegalCSRAccessM, .BigEndianM,
.DebugCapture, .DebugScanEn, .DebugScanIn, .DebugScanOut);
// pipeline early-arriving trap sources // pipeline early-arriving trap sources
privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,