From 5b50fcd4f4adacbbeaff6f34531d800bb9714d53 Mon Sep 17 00:00:00 2001 From: James Stine Date: Tue, 4 Jun 2024 09:25:41 -0500 Subject: [PATCH] update two files tha thad repeated lines in them --- src/privileged/csr.sv | 2 -- src/privileged/privileged.sv | 2 -- 2 files changed, 4 deletions(-) diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index d29803cd4..23f9860dd 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -242,8 +242,6 @@ module csr import cvw::*; #(parameter cvw_t P) ( .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM, .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM, .MENVCFG_REGW, .DebugCapture, .DebugScanEn, .DebugScanIn, .DebugScanOut); - .MENVCFG_REGW, .DebugCapture, .DebugScanEn, .DebugScanIn, .DebugScanOut); - if (P.S_SUPPORTED) begin:csrs logic STCE; diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index b4b891796..9c8cc40e9 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -154,8 +154,6 @@ module privileged import cvw::*; #(parameter cvw_t P) ( .EPCM, .TrapVectorM, .CSRReadValW, .IllegalCSRAccessM, .BigEndianM, .DebugCapture, .DebugScanEn, .DebugScanIn, .DebugScanOut); - .CSRReadValW, .IllegalCSRAccessM, .BigEndianM, - .DebugCapture, .DebugScanEn, .DebugScanIn, .DebugScanOut); // pipeline early-arriving trap sources privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,