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Fixed lint errors in loggers.sv with Kaitlin.

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This commit is contained in:
Rose Thompson 2024-11-12 15:03:30 -06:00
parent de394d760f
commit 57fbd35484
1 changed files with 12 additions and 5 deletions
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17
testbench/common/loggers.sv
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@ -46,11 +46,11 @@ module loggers import cvw::*; #(parameter cvw_t P,
// performance counter logging // performance counter logging
logic BeginSample; logic BeginSample;
logic StartSample, EndSample; logic StartSample, EndSample;
if((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED) begin : HPMCSample if((PrintHPMCounters || BPRED_LOGGER) && P.ZICNTR_SUPPORTED) begin : HPMCSample
integer HPMCindex; integer HPMCindex;
logic StartSampleFirst; logic StartSampleFirst;
logic StartSampleDelayed, BeginDelayed; logic StartSampleDelayed, BeginDelayed;
logic EndSampleFirst, EndSampleDelayed; logic EndSampleFirst;
logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0]; logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0];
string HPMCnames[] = '{"Mcycle", string HPMCnames[] = '{"Mcycle",
@ -89,9 +89,18 @@ module loggers import cvw::*; #(parameter cvw_t P,
EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time"; EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
end else begin end else begin
StartSampleFirst = reset; StartSampleFirst = reset;
EndSample = DCacheFlushStart & ~DCacheFlushDone; EndSampleFirst = '0;
end end
// this code needs to be with embench and coremark but not the else condition
if (TEST == "embench" | TEST == "coremark") begin
logic EndSampleDelayed;
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
end else begin
assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
end
/* /*
if(TEST == "embench") begin if(TEST == "embench") begin
// embench runs warmup then runs start_trigger // embench runs warmup then runs start_trigger
@ -132,8 +141,6 @@ module loggers import cvw::*; #(parameter cvw_t P,
flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
assign StartSample = StartSampleFirst & ~StartSampleDelayed; assign StartSample = StartSampleFirst & ~StartSampleDelayed;
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); // ** is this redundant with StartSampleReg? flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); // ** is this redundant with StartSampleReg?
assign BeginSample = StartSampleFirst & ~BeginDelayed; assign BeginSample = StartSampleFirst & ~BeginDelayed;