From 57fbd354842c60e4b6712cd84c33075dd7a606f2 Mon Sep 17 00:00:00 2001
From: Rose Thompson <rose@rosethompson.net>
Date: Tue, 12 Nov 2024 15:03:30 -0600
Subject: [PATCH] Fixed lint errors in loggers.sv with Kaitlin.

---
 testbench/common/loggers.sv | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv
index 6b026257a..89fe59ca8 100644
--- a/testbench/common/loggers.sv
+++ b/testbench/common/loggers.sv
@@ -46,11 +46,11 @@ module loggers import cvw::*; #(parameter cvw_t P,
   // performance counter logging 
   logic        BeginSample;
   logic StartSample, EndSample;
-  if((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED) begin : HPMCSample
+  if((PrintHPMCounters || BPRED_LOGGER) && P.ZICNTR_SUPPORTED) begin : HPMCSample
     integer           HPMCindex;
     logic             StartSampleFirst;
     logic             StartSampleDelayed, BeginDelayed;
-    logic             EndSampleFirst, EndSampleDelayed;
+    logic             EndSampleFirst;
     logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0];
 
     string  HPMCnames[] = '{"Mcycle",
@@ -89,9 +89,18 @@ module loggers import cvw::*; #(parameter cvw_t P,
         EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
       end else begin
         StartSampleFirst = reset;
-        EndSample = DCacheFlushStart & ~DCacheFlushDone;
+        EndSampleFirst = '0;
       end
 
+    // this code needs to be with embench and coremark but not the else condition
+    if (TEST == "embench" | TEST == "coremark") begin
+      logic EndSampleDelayed;
+      flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
+      assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
+    end else begin
+      assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
+    end
+    
   /*
     if(TEST == "embench") begin
       // embench runs warmup then runs start_trigger
@@ -132,8 +141,6 @@ module loggers import cvw::*; #(parameter cvw_t P,
 
     flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
     assign StartSample = StartSampleFirst & ~StartSampleDelayed;
-    flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
-    assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
     flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); // ** is this redundant with StartSampleReg?
     assign BeginSample = StartSampleFirst & ~BeginDelayed;