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Merging PR738

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This commit is contained in:
David Harris 2024-04-20 17:15:17 -07:00
commit 571b67f565
4 changed files with 142 additions and 132 deletions
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86
bin/regression-wally
View File

@ -12,7 +12,6 @@
################################## ##################################
import sys,os,shutil import sys,os,shutil
import multiprocessing import multiprocessing
#import os
from collections import namedtuple from collections import namedtuple
from multiprocessing import Pool, TimeoutError from multiprocessing import Pool, TimeoutError
@ -24,7 +23,6 @@ from multiprocessing import Pool, TimeoutError
# The element consists of the configuration name, a list of test suites to run, # The element consists of the configuration name, a list of test suites to run,
# optionally a string to pass to the simulator, and optionally a nonstandard grep string to check for success # optionally a string to pass to the simulator, and optionally a nonstandard grep string to check for success
INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
tests = [ tests = [
["rv32e", ["arch32e"]], ["rv32e", ["arch32e"]],
["rv32i", ["arch32i"]], ["rv32i", ["arch32i"]],
@ -34,10 +32,22 @@ tests = [
"arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma",
"arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zcb", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zcb",
"arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], # "arch32zfad" # fcvtmod.w.d not working because of Sail flag bug. Jordan has PR in to fix Sail "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], # "arch32zfad" # fcvtmod.w.d not working because of Sail flag bug. Jordan has PR in to fix Sail
["rv64i", ["arch64i"]], ["rv64i", ["arch64i"]]
["buildroot", ["buildroot"], [f"+INSTR_LIMIT={INSTR_LIMIT}"], str(INSTR_LIMIT)+" instructions"]
] ]
# Separate test for full buildroot run
tests_buildrootshort = [
["buildroot", ["buildroot"], [f"+INSTR_LIMIT=1400000"], # Instruction limit gets to first OpenSBI UART output
"OpenSBI v", "buildroot_uart.out"]
]
tests_buildrootboot = [
["buildroot", ["buildroot"], [f"+INSTR_LIMIT=600000000"], # boot entire buildroot Linux to login prompt
"WallyHostname login: ", "buildroot_uart.out"]
]
# Separate out floating-point tests for RV64 to speed up coverage # Separate out floating-point tests for RV64 to speed up coverage
tests64gc_nofp = [ tests64gc_nofp = [
["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb", ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb",
@ -176,7 +186,7 @@ bpredtests = [
# Data Types & Functions # Data Types & Functions
################################## ##################################
TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfile'])
# name: the name of this test configuration (used in printing human-readable # name: the name of this test configuration (used in printing human-readable
# output and picking logfile names) # output and picking logfile names)
# cmd: the command to run to test (should include the logfile as '{}', and # cmd: the command to run to test (should include the logfile as '{}', and
@ -184,6 +194,7 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
# grepstr: the string to grep through the log file for. The test succeeds iff # grepstr: the string to grep through the log file for. The test succeeds iff
# grep finds that string in the logfile (is used by grep, so it may # grep finds that string in the logfile (is used by grep, so it may
# be any pattern grep accepts, see `man 1 grep` for more info). # be any pattern grep accepts, see `man 1 grep` for more info).
# grepfile: a string containing the location of the file to be searched for output
class bcolors: class bcolors:
HEADER = '\033[95m' HEADER = '\033[95m'
@ -197,6 +208,7 @@ class bcolors:
UNDERLINE = '\033[4m' UNDERLINE = '\033[4m'
def addTests(tests, sim): def addTests(tests, sim):
sim_logdir = WALLY+ "/sim/" + sim + "/logs/"
for test in tests: for test in tests:
config = test[0]; config = test[0];
suites = test[1]; suites = test[1];
@ -210,36 +222,38 @@ def addTests(tests, sim):
gs = "All tests ran without failures" gs = "All tests ran without failures"
cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config
for t in suites: for t in suites:
sim_log = sim_logdir + config + "_" + t + ".log"
if (len(test) >= 5):
grepfile = sim_logdir + test[4]
else:
grepfile = sim_log
tc = TestCase( tc = TestCase(
name=t, name=t,
variant=config, variant=config,
cmd=cmdPrefix + " " + t + args, cmd=cmdPrefix + " " + t + args + " > " + sim_log,
grepstr=gs) grepstr=gs,
grepfile = grepfile)
configs.append(tc) configs.append(tc)
def search_log_for_text(text, logfile): def search_log_for_text(text, grepfile):
"""Search through the given log file for text, returning True if it is found or False if it is not""" """Search through the given log file for text, returning True if it is found or False if it is not"""
grepcmd = "grep -e '%s' '%s' > /dev/null" % (text, logfile) grepcmd = "grep -a -e '%s' '%s' > /dev/null" % (text, grepfile)
# print(" search_log_for_text invoking %s" % grepcmd) # print(" search_log_for_text invoking %s" % grepcmd)
return os.system(grepcmd) == 0 return os.system(grepcmd) == 0
def run_test_case(config): def run_test_case(config):
"""Run the given test case, and return 0 if the test suceeds and 1 if it fails""" """Run the given test case, and return 0 if the test suceeds and 1 if it fails"""
logname = WALLY + "/sim/questa/logs/"+config.variant+"_"+config.name+".log" ### *** fix hardwiring to questa log grepfile = config.grepfile
#cmd = config.cmd + " > " + logname cmd = config.cmd
if ("lint-wally" in config.cmd):
cmd = config.cmd + " | tee " + logname
else:
cmd = config.cmd + " > " + logname
os.chdir(regressionDir) os.chdir(regressionDir)
# print(" run_test_case invoking %s" % cmd) # print(" run_test_case invoking %s" % cmd)
os.system(cmd) os.system(cmd)
if search_log_for_text(config.grepstr, logname): if search_log_for_text(config.grepstr, grepfile):
print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name)) print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name))
return 0 return 0
else: else:
print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name)) print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name))
print(" Check %s" % logname) print(" Check %s" % grepfile)
return 1 return 1
################################## ##################################
@ -258,13 +272,14 @@ coverage = '--coverage' in sys.argv
fp = '--fp' in sys.argv fp = '--fp' in sys.argv
nightly = '--nightly' in sys.argv nightly = '--nightly' in sys.argv
testfloat = '--testfloat' in sys.argv testfloat = '--testfloat' in sys.argv
buildroot = '--buildroot' in sys.argv
if (nightly): if (nightly):
nightMode = "--nightly"; nightMode = "--nightly";
# sims = ["questa", "verilator", "vcs"] # sims = ["questa", "verilator", "vcs"]
sims = ["verilator"] # *** uncomment to exercise all simulators sims = ["verilator"] # *** uncomment to exercise all simulators
else: else:
nightMode = ""; nightMode = ""
sims = [defaultsim] sims = [defaultsim]
if (coverage): # only run RV64GC tests in coverage mode if (coverage): # only run RV64GC tests in coverage mode
@ -278,9 +293,9 @@ configs = [
TestCase( TestCase(
name="lints", name="lints",
variant="all", variant="all",
cmd="lint-wally " + nightMode, cmd="lint-wally " + nightMode + " | tee " + WALLY + "/sim/questa/logs/all_lints.log",
grepstr="lints run with no errors or warnings" grepstr="lints run with no errors or warnings",
) grepfile = WALLY + "/sim/questa/logs/all_lints.log")
] ]
if (coverage): # only run RV64GC tests on Questa in coverage mode if (coverage): # only run RV64GC tests on Questa in coverage mode
@ -292,9 +307,13 @@ else:
addTests(tests, sim) addTests(tests, sim)
addTests(tests64gc_nofp, sim) addTests(tests64gc_nofp, sim)
addTests(tests64gc_fp, sim) addTests(tests64gc_fp, sim)
# run derivative configurations in nightly regression # run derivative configurations in nightly regression
if (nightly): if (nightly):
addTests(derivconfigtests, defaultsim) addTests(derivconfigtests, defaultsim)
addTests(tests_buildrootboot, defaultsim)
else:
addTests(tests_buildrootshort, defaultsim)
# testfloat tests # testfloat tests
if (testfloat): if (testfloat):
@ -306,11 +325,13 @@ if (testfloat):
if ("f_" in config): if ("f_" in config):
tests.remove("cvtfp") tests.remove("cvtfp")
for test in tests: for test in tests:
sim_log = WALLY + "/sim/questa/logs/"+config+"_"+test+".log" # TODO: Change hardcoded questa log directory to simulator
tc = TestCase( tc = TestCase(
name=test, name=test,
variant=config, variant=config,
cmd="wsim --tb testbench_fp " + config + " " + test, cmd="wsim --tb testbench_fp " + config + " " + test + " > " + sim_log,
grepstr="All Tests completed with 0 errors") grepstr="All Tests completed with 0 errors",
grepfile = sim_log)
configs.append(tc) configs.append(tc)
@ -349,11 +370,13 @@ if (testfloat):
if ("f_" in config): if ("f_" in config):
tests.remove("cvtfp") tests.remove("cvtfp")
for test in tests: for test in tests:
sim_log = WALLY + "/sim/questa/logs/"+config+"_"+test+".log"
tc = TestCase( tc = TestCase(
name=test, name=test,
variant=config, variant=config,
cmd="wsim --tb testbench_fp --sim questa " + config + " " + test, cmd="wsim --tb testbench_fp --sim questa " + config + " " + test + " > " + sim_log,
grepstr="All Tests completed with 0 errors") grepstr="All Tests completed with 0 errors",
grepfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log")
configs.append(tc) configs.append(tc)
@ -371,26 +394,17 @@ def main():
os.chdir(regressionDir) os.chdir(regressionDir)
os.system('./make-tests.sh | tee ./logs/make-tests.log') os.system('./make-tests.sh | tee ./logs/make-tests.log')
if '--all' in sys.argv: if '--buildroot' in sys.argv:
TIMEOUT_DUR = 30*7200 # seconds TIMEOUT_DUR = 60*7200 # 5 days to run
#configs.append(getBuildrootTC(boot=True))
elif '--buildroot' in sys.argv:
TIMEOUT_DUR = 30*7200 # seconds
#configs=[getBuildrootTC(boot=True)]
elif '--coverage' in sys.argv: elif '--coverage' in sys.argv:
TIMEOUT_DUR = 20*60 # seconds TIMEOUT_DUR = 20*60 # seconds
# Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage.
# Also it is slow to run.
# configs.append(getBuildrootTC(boot=False))
os.system('rm -f questa/cov/*.ucdb') os.system('rm -f questa/cov/*.ucdb')
elif '--nightly' in sys.argv: elif '--nightly' in sys.argv:
TIMEOUT_DUR = 60*1440 # 1 day TIMEOUT_DUR = 60*1440 # 1 day
#configs.append(getBuildrootTC(boot=False))
elif '--testfloat' in sys.argv: elif '--testfloat' in sys.argv:
TIMEOUT_DUR = 5*60 # seconds TIMEOUT_DUR = 5*60 # seconds
else: else:
TIMEOUT_DUR = 10*60 # seconds TIMEOUT_DUR = 10*60 # seconds
#configs.append(getBuildrootTC(boot=False))
# Scale the number of concurrent processes to the number of test cases, but # Scale the number of concurrent processes to the number of test cases, but
# max out at a limited number of concurrent processes to not overwhelm the system # max out at a limited number of concurrent processes to not overwhelm the system

164
sim/questa/wave.do
View File

@ -471,88 +471,88 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HADDR add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HADDR
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HTRANS add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HTRANS
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HREADY add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HREADY
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELRegions
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELNoneD
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELPLICD
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HRDATA
add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/UARTIntr
add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/GPIOIntr
add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/MExtInt
add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/SExtInt add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/SExtInt
add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/Dout add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/Dout
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intClaim
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intEn add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intEn
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intInProgress add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intInProgress
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPending add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intPending
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPriority add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intPriority
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intThreshold add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intThreshold
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/nextIntPending add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/nextIntPending
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/requests add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/requests
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqMatrix add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/irqMatrix
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/priorities_with_irqs add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/priorities_with_irqs
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/max_priority_with_irqs
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/irqs_at_max_priority
add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/threshMask
add wave -noupdate -group uncore -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME add wave -noupdate -group uncore -group CLINT /testbench/dut/uncoregen/uncore/clint/clint/MTIME
add wave -noupdate -group uncore -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP add wave -noupdate -group uncore -group CLINT /testbench/dut/uncoregen/uncore/clint/clint/MTIMECMP
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSEL add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PSEL
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PADDR add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PADDR
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWDATA add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PWDATA
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSTRB add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PSTRB
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWRITE add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PWRITE
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PENABLE add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PENABLE
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PRDATA add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PRDATA
add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PREADY add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PREADY
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LSR add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/LSR
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MCR add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/MCR
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MSR add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/MSR
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/RBR add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/RBR
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/TXHR add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/TXHR
add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LCR add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/LCR
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/intrID add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/intrID
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/INTR add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/INTR
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxstate add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxstate
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txstate add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txstate
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitssent add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txbitssent
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitsexpected add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txbitsexpected
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsreceived add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxbitsreceived
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsexpected add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxbitsexpected
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdata add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdata
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxoverrunerr add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxoverrunerr
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataready add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdataready
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataavailintr add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdataavailintr
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/RXBR add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/RXBR
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/squashRXerrIP add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/squashRXerrIP
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxshiftreg add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxshiftreg
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/SOUTbit add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/SOUTbit
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/SINsync add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/SINsync
add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txsr add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txsr
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SIN add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/SIN
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SOUT add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/SOUT
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RTSb add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/RTSb
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DTRb add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DTRb
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT1b add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/OUT1b
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT2b add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/OUT2b
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DSRb add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DSRb
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DCDb add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DCDb
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/CTSb add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/CTSb
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/TXRDYb add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/TXRDYb
add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RXRDYb add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/RXRDYb
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIN add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOIN
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOOUT add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOOUT
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOEN add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOEN
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOIntr
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PSEL
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PADDR
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PWRITE
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PRDATA
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PREADY
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PWDATA
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PSTRB
add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PENABLE
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rf add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rf
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2

1
src/generic/mem/rom1p1r.sv
View File

@ -31,7 +31,6 @@ import "DPI-C" function string getenvval(input string env_name);
`else `else
import "DPI-C" function string getenv(input string env_name); import "DPI-C" function string getenv(input string env_name);
`endif `endif
import "DPI-C" function int system(input string env_name);
module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
(input logic clk, (input logic clk,

15
testbench/testbench.sv
View File

@ -39,7 +39,6 @@ import "DPI-C" function string getenvval(input string env_name);
`else `else
import "DPI-C" function string getenv(input string env_name); import "DPI-C" function string getenv(input string env_name);
`endif `endif
import "DPI-C" function int system(input string env_name);
module testbench; module testbench;
/* verilator lint_off WIDTHTRUNC */ /* verilator lint_off WIDTHTRUNC */
@ -254,8 +253,9 @@ module testbench;
logic ResetCntRst; logic ResetCntRst;
logic CopyRAM; logic CopyRAM;
string signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd; string signame, memfilename, bootmemfilename, uartoutfilename, pathname;
integer begin_signature_addr, end_signature_addr, signature_size; integer begin_signature_addr, end_signature_addr, signature_size;
integer uartoutfile;
assign ResetThreshold = 3'd5; assign ResetThreshold = 3'd5;
@ -328,8 +328,6 @@ module testbench;
else else
assign EcallFaultM = 0; assign EcallFaultM = 0;
// this is an unused integer for the return value of `system`
int unused_int;
always @(posedge clk) begin always @(posedge clk) begin
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Verify the test ran correctly by checking the memory against a known signature. // Verify the test ran correctly by checking the memory against a known signature.
@ -355,8 +353,7 @@ module testbench;
memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"}; memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
uartoutfilename = {"logs/", TEST, "_uart.out"}; uartoutfilename = {"logs/", TEST, "_uart.out"};
rmCmd = {"rm -f ", uartoutfilename}; uartoutfile = $fopen(uartoutfilename, "wb");
unused_int = system(rmCmd); // Delete existing UARToutfile
end end
else memfilename = {pathname, tests[test], ".elf.memfile"}; else memfilename = {pathname, tests[test], ".elf.memfile"};
if (riscofTest) begin if (riscofTest) begin
@ -383,6 +380,8 @@ module testbench;
always @(posedge Validate) // added always @(posedge Validate) // added
`endif `endif
if(Validate) begin if(Validate) begin
if (TEST == "buildroot")
$fclose(uartoutfile);
if (TEST == "embench") begin if (TEST == "embench") begin
// Writes contents of begin_signature to .sim.output file // Writes contents of begin_signature to .sim.output file
// this contains instret and cycles for start and end of test run, used by embench // this contains instret and cycles for start and end of test run, used by embench
@ -602,9 +601,7 @@ module testbench;
always @(posedge clk) begin always @(posedge clk) begin
if (TEST == "buildroot") begin if (TEST == "buildroot") begin
if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin
memFile = $fopen(uartoutfilename, "ab"); $fwrite(uartoutfile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din);
$fwrite(memFile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din);
$fclose(memFile);
end end
end end
end end