From 554f818a8c0a72ed0a214ef734c286f0ae454df6 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 16 Apr 2024 14:43:38 -0700 Subject: [PATCH 1/9] Fixed wave.do to match new conditional generate block names --- sim/questa/wave.do | 164 ++++++++++++++++++++++----------------------- 1 file changed, 82 insertions(+), 82 deletions(-) diff --git a/sim/questa/wave.do b/sim/questa/wave.do index bb6b1d54b..9947bcd6f 100644 --- a/sim/questa/wave.do +++ b/sim/questa/wave.do @@ -471,88 +471,88 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK -add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HADDR -add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HTRANS -add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HREADY -add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions -add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD -add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD -add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA -add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr -add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr -add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt -add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/SExtInt -add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/Dout -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intEn -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intInProgress -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPending -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPriority -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intThreshold -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/nextIntPending -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/requests -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqMatrix -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/priorities_with_irqs -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority -add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask -add wave -noupdate -group uncore -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME -add wave -noupdate -group uncore -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSEL -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PADDR -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWDATA -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSTRB -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWRITE -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PENABLE -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PRDATA -add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PREADY -add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LSR -add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MCR -add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MSR -add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/RBR -add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/TXHR -add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LCR -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/intrID -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/INTR -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxstate -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txstate -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitssent -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitsexpected -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsreceived -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsexpected -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdata -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxoverrunerr -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataready -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataavailintr -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/RXBR -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/squashRXerrIP -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxshiftreg -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/SOUTbit -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/SINsync -add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txsr -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SIN -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SOUT -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RTSb -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DTRb -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT1b -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT2b -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DSRb -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DCDb -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/CTSb -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/TXRDYb -add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RXRDYb -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIN -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOOUT -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOEN -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB -add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE +add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HADDR +add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HTRANS +add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HREADY +add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELRegions +add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELNoneD +add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELPLICD +add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HRDATA +add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/UARTIntr +add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/GPIOIntr +add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/MExtInt +add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/SExtInt +add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/Dout +add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intClaim +add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intEn +add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intInProgress +add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intPending +add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intPriority +add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intThreshold +add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/nextIntPending +add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/requests +add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/irqMatrix +add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/priorities_with_irqs +add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/max_priority_with_irqs +add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/irqs_at_max_priority +add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/threshMask +add wave -noupdate -group uncore -group CLINT /testbench/dut/uncoregen/uncore/clint/clint/MTIME +add wave -noupdate -group uncore -group CLINT /testbench/dut/uncoregen/uncore/clint/clint/MTIMECMP +add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PSEL +add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PADDR +add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PWDATA +add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PSTRB +add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PWRITE +add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PENABLE +add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PRDATA +add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PREADY +add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/LSR +add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/MCR +add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/MSR +add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/RBR +add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/TXHR +add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/LCR +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/intrID +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/INTR +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxstate +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txstate +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txbitssent +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txbitsexpected +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxbitsreceived +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxbitsexpected +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdata +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxoverrunerr +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdataready +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdataavailintr +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/RXBR +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/squashRXerrIP +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxshiftreg +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/SOUTbit +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/SINsync +add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txsr +add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/SIN +add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/SOUT +add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/RTSb +add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DTRb +add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/OUT1b +add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/OUT2b +add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DSRb +add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DCDb +add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/CTSb +add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/TXRDYb +add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/RXRDYb +add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOIN +add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOOUT +add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOEN +add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOIntr +add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PSEL +add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PADDR +add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PWRITE +add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PRDATA +add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PREADY +add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PWDATA +add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PSTRB +add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PENABLE add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rf add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2 From 48a2028891370fcc1adb6e2c54f0e996c5c5eec4 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 16 Apr 2024 17:27:25 -0700 Subject: [PATCH 2/9] Added --buildroot option to run a full Linux boot and search 'buildroot_uart.out' for login prompt --- bin/regression-wally | 49 ++++++++++++++++++++++++++++++++++---------- 1 file changed, 38 insertions(+), 11 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index bdb58fea0..a03c0b0bb 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -12,7 +12,6 @@ ################################## import sys,os,shutil import multiprocessing -#import os from collections import namedtuple from multiprocessing import Pool, TimeoutError @@ -24,7 +23,7 @@ from multiprocessing import Pool, TimeoutError # The element consists of the configuration name, a list of test suites to run, # optionally a string to pass to the simulator, and optionally a nonstandard grep string to check for success -INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM +INSTR_LIMIT = 4000000 # multiple of 100000; Set to 0 to run simulation until timeout or Wally Hostname: tests = [ ["rv32e", ["arch32e"]], ["rv32i", ["arch32i"]], @@ -38,6 +37,11 @@ tests = [ ["buildroot", ["buildroot"], [f"+INSTR_LIMIT={INSTR_LIMIT}"], str(INSTR_LIMIT)+" instructions"] ] + +# Separate test for full buildroot run +tests_buildroot = [["buildroot", ["buildroot"], [f"+INSTR_LIMIT=600000000"], "WallyHostName login:", os.environ.get('WALLY')+"/sim/questa/logs/buildroot_uart.out"]] + + # Separate out floating-point tests for RV64 to speed up coverage tests64gc_nofp = [ ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", @@ -176,7 +180,7 @@ bpredtests = [ # Data Types & Functions ################################## -TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) +TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'logfile', 'overwrite']) # name: the name of this test configuration (used in printing human-readable # output and picking logfile names) # cmd: the command to run to test (should include the logfile as '{}', and @@ -184,6 +188,7 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) # grepstr: the string to grep through the log file for. The test succeeds iff # grep finds that string in the logfile (is used by grep, so it may # be any pattern grep accepts, see `man 1 grep` for more info). +# logfile: the string corresponding to the log file for the test. autogenerated class bcolors: HEADER = '\033[95m' @@ -210,11 +215,19 @@ def addTests(tests, sim): gs = "All tests ran without failures" cmdPrefix="wsim --sim " + sim + " " + config for t in suites: + if (len(test) >= 5): + logfile = test[4] + overwrite = 0 + else: + logfile = WALLY + "/sim/"+sim+"/logs/"+config+"_"+t+".log" + overwrite = 1 tc = TestCase( name=t, variant=config, cmd=cmdPrefix + " " + t + args, - grepstr=gs) + grepstr=gs, + logfile = logfile, + overwrite = overwrite) configs.append(tc) def search_log_for_text(text, logfile): @@ -225,14 +238,17 @@ def search_log_for_text(text, logfile): def run_test_case(config): """Run the given test case, and return 0 if the test suceeds and 1 if it fails""" - logname = WALLY + "/sim/questa/logs/"+config.variant+"_"+config.name+".log" ### *** fix hardwiring to questa log + logname = config.logfile + WALLY = os.environ.get('WALLY') #cmd = config.cmd + " > " + logname if ("lint-wally" in config.cmd): cmd = config.cmd + " | tee " + logname + elif (config.overwrite == 0): ### TODO: Fix hardcoding for logs/buildroot_buildroot.log + cmd = config.cmd + f" > {WALLY}/sim/questa/logs/buildroot_buildroot.log" else: cmd = config.cmd + " > " + logname os.chdir(regressionDir) -# print(" run_test_case invoking %s" % cmd) + # print(" run_test_case invoking %s" % cmd) os.system(cmd) if search_log_for_text(config.grepstr, logname): print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name)) @@ -258,6 +274,7 @@ coverage = '--coverage' in sys.argv fp = '--fp' in sys.argv nightly = '--nightly' in sys.argv testfloat = '--testfloat' in sys.argv +buildroot = '--buildroot' in sys.argv if (nightly): nightMode = "--nightly"; @@ -278,15 +295,21 @@ configs = [ name="lints", variant="all", cmd="lint-wally " + nightMode, - grepstr="lints run with no errors or warnings" + grepstr="lints run with no errors or warnings", + logfile = WALLY + "/sim/questa/logs/all_lints.log", + overwrite = 1 ) ] +if (buildroot): + for sim in sims: + addTests(tests_buildroot, sim) + if (coverage): # only run RV64GC tests on Questa in coverage mode addTests(tests64gc_nofp, "questa") if (fp): addTests(tests64gc_fp, "questa") -else: +elif not buildroot: for sim in sims: addTests(tests, sim) addTests(tests64gc_nofp, sim) @@ -309,7 +332,9 @@ if (testfloat): name=test, variant=config, cmd="wsim --tb testbench_fp " + config + " " + test, - grepstr="All Tests completed with 0 errors") + grepstr="All Tests completed with 0 errors", + logfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log", + overwrite = 1) configs.append(tc) @@ -352,7 +377,9 @@ if (testfloat): name=test, variant=config, cmd="wsim --tb testbench_fp --sim questa " + config + " " + test, - grepstr="All Tests completed with 0 errors") + grepstr="All Tests completed with 0 errors", + logfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log", + overwrite = 1) configs.append(tc) @@ -374,7 +401,7 @@ def main(): TIMEOUT_DUR = 30*7200 # seconds #configs.append(getBuildrootTC(boot=True)) elif '--buildroot' in sys.argv: - TIMEOUT_DUR = 30*7200 # seconds + TIMEOUT_DUR = 60*7200 # 5 days to run #configs=[getBuildrootTC(boot=True)] elif '--coverage' in sys.argv: TIMEOUT_DUR = 20*60 # seconds From b5ef66dc3c6e7018200188ef15c17c20216cf6e3 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 17 Apr 2024 10:26:30 -0700 Subject: [PATCH 3/9] Less hacky implementation of the same method as before --- bin/regression-wally | 47 +++++++++++++++++++------------------------- 1 file changed, 20 insertions(+), 27 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index a03c0b0bb..d80b25da0 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -23,7 +23,7 @@ from multiprocessing import Pool, TimeoutError # The element consists of the configuration name, a list of test suites to run, # optionally a string to pass to the simulator, and optionally a nonstandard grep string to check for success -INSTR_LIMIT = 4000000 # multiple of 100000; Set to 0 to run simulation until timeout or Wally Hostname: +INSTR_LIMIT = 400000 # multiple of 100000; Set to 0 to run simulation until timeout or Wally Hostname: tests = [ ["rv32e", ["arch32e"]], ["rv32i", ["arch32i"]], @@ -39,7 +39,10 @@ tests = [ # Separate test for full buildroot run -tests_buildroot = [["buildroot", ["buildroot"], [f"+INSTR_LIMIT=600000000"], "WallyHostName login:", os.environ.get('WALLY')+"/sim/questa/logs/buildroot_uart.out"]] +tests_buildrootboot = [ + ["buildroot", ["buildroot"], [f"+INSTR_LIMIT=600000000"], + "WallyHostname login: ", os.environ.get('WALLY')+"/sim/questa/logs/buildroot_uart.out"] + ] # Separate out floating-point tests for RV64 to speed up coverage @@ -180,7 +183,7 @@ bpredtests = [ # Data Types & Functions ################################## -TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'logfile', 'overwrite']) +TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'logfile']) # name: the name of this test configuration (used in printing human-readable # output and picking logfile names) # cmd: the command to run to test (should include the logfile as '{}', and @@ -188,7 +191,7 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'logfile # grepstr: the string to grep through the log file for. The test succeeds iff # grep finds that string in the logfile (is used by grep, so it may # be any pattern grep accepts, see `man 1 grep` for more info). -# logfile: the string corresponding to the log file for the test. autogenerated +# logfile: a string containing the location of the logfile. class bcolors: HEADER = '\033[95m' @@ -202,6 +205,7 @@ class bcolors: UNDERLINE = '\033[4m' def addTests(tests, sim): + sim_logdir = WALLY+ "/sim/" + sim + "/logs/" for test in tests: config = test[0]; suites = test[1]; @@ -213,21 +217,19 @@ def addTests(tests, sim): gs = test[3] else: gs = "All tests ran without failures" - cmdPrefix="wsim --sim " + sim + " " + config + cmdPrefix="wsim --sim " + sim + " " + config for t in suites: + sim_log = sim_logdir + config + "_" + t + ".log" if (len(test) >= 5): logfile = test[4] - overwrite = 0 else: - logfile = WALLY + "/sim/"+sim+"/logs/"+config+"_"+t+".log" - overwrite = 1 + logfile = sim_log tc = TestCase( name=t, variant=config, - cmd=cmdPrefix + " " + t + args, + cmd=cmdPrefix + " " + t + args + " > " + sim_log, grepstr=gs, - logfile = logfile, - overwrite = overwrite) + logfile = logfile) configs.append(tc) def search_log_for_text(text, logfile): @@ -239,14 +241,7 @@ def search_log_for_text(text, logfile): def run_test_case(config): """Run the given test case, and return 0 if the test suceeds and 1 if it fails""" logname = config.logfile - WALLY = os.environ.get('WALLY') - #cmd = config.cmd + " > " + logname - if ("lint-wally" in config.cmd): - cmd = config.cmd + " | tee " + logname - elif (config.overwrite == 0): ### TODO: Fix hardcoding for logs/buildroot_buildroot.log - cmd = config.cmd + f" > {WALLY}/sim/questa/logs/buildroot_buildroot.log" - else: - cmd = config.cmd + " > " + logname + cmd = config.cmd os.chdir(regressionDir) # print(" run_test_case invoking %s" % cmd) os.system(cmd) @@ -294,16 +289,14 @@ configs = [ TestCase( name="lints", variant="all", - cmd="lint-wally " + nightMode, + cmd="lint-wally " + nightMode + " | tee " + WALLY + "/sim/questa/logs/all_lints.log", grepstr="lints run with no errors or warnings", - logfile = WALLY + "/sim/questa/logs/all_lints.log", - overwrite = 1 - ) + logfile = WALLY + "/sim/questa/logs/all_lints.log") ] if (buildroot): for sim in sims: - addTests(tests_buildroot, sim) + addTests(tests_buildrootboot, sim) if (coverage): # only run RV64GC tests on Questa in coverage mode addTests(tests64gc_nofp, "questa") @@ -328,13 +321,13 @@ if (testfloat): if ("f_" in config): tests.remove("cvtfp") for test in tests: + sim_log = WALLY + "/sim/questa/logs/"+config+"_"+test+".log" tc = TestCase( name=test, variant=config, - cmd="wsim --tb testbench_fp " + config + " " + test, + cmd="wsim --tb testbench_fp " + config + " " + test + " > " + sim_log, grepstr="All Tests completed with 0 errors", - logfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log", - overwrite = 1) + logfile = sim_log) configs.append(tc) From d39f1ebefca32838a7b6be242e6fe6ed96acd86b Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 17 Apr 2024 10:41:12 -0700 Subject: [PATCH 4/9] Less hacky implementation of simulation log and searched log --- bin/regression-wally | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index d80b25da0..6dab7e8b0 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -366,13 +366,13 @@ if (testfloat): if ("f_" in config): tests.remove("cvtfp") for test in tests: + sim_log = WALLY + "/sim/questa/logs/"+config+"_"+test+".log" tc = TestCase( name=test, variant=config, - cmd="wsim --tb testbench_fp --sim questa " + config + " " + test, + cmd="wsim --tb testbench_fp --sim questa " + config + " " + test + " > " + sim_log, grepstr="All Tests completed with 0 errors", - logfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log", - overwrite = 1) + logfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log") configs.append(tc) From 04ac4007ec5e7cb7f66e2b1aba437cd0bc5e5916 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Sat, 20 Apr 2024 16:08:08 -0700 Subject: [PATCH 5/9] Updated tuple to name logfile to grepfile to better reflect purpose in regression. Added -a to grep so it works iwth binary files --- bin/regression-wally | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 2c5ff401b..c7f406e25 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -23,7 +23,7 @@ from multiprocessing import Pool, TimeoutError # The element consists of the configuration name, a list of test suites to run, # optionally a string to pass to the simulator, and optionally a nonstandard grep string to check for success -INSTR_LIMIT = 400000 # multiple of 100000; Set to 0 to run simulation until timeout or Wally Hostname: +INSTR_LIMIT = 1300000 # multiple of 100000; Set to 0 to run simulation until timeout or Wally Hostname: tests = [ ["rv32e", ["arch32e"]], ["rv32i", ["arch32i"]], @@ -183,7 +183,7 @@ bpredtests = [ # Data Types & Functions ################################## -TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'logfile']) +TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfile']) # name: the name of this test configuration (used in printing human-readable # output and picking logfile names) # cmd: the command to run to test (should include the logfile as '{}', and @@ -191,7 +191,7 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'logfile # grepstr: the string to grep through the log file for. The test succeeds iff # grep finds that string in the logfile (is used by grep, so it may # be any pattern grep accepts, see `man 1 grep` for more info). -# logfile: a string containing the location of the logfile. +# grepfile: a string containing the location of the file to be searched for output class bcolors: HEADER = '\033[95m' @@ -221,36 +221,36 @@ def addTests(tests, sim): for t in suites: sim_log = sim_logdir + config + "_" + t + ".log" if (len(test) >= 5): - logfile = test[4] + grepfile = test[4] else: - logfile = sim_log + grepfile = sim_log tc = TestCase( name=t, variant=config, cmd=cmdPrefix + " " + t + args + " > " + sim_log, grepstr=gs, - logfile = logfile) + grepfile = grepfile) configs.append(tc) -def search_log_for_text(text, logfile): +def search_log_for_text(text, grepfile): """Search through the given log file for text, returning True if it is found or False if it is not""" - grepcmd = "grep -e '%s' '%s' > /dev/null" % (text, logfile) + grepcmd = "grep -a -e '%s' '%s' > /dev/null" % (text, grepfile) # print(" search_log_for_text invoking %s" % grepcmd) return os.system(grepcmd) == 0 def run_test_case(config): """Run the given test case, and return 0 if the test suceeds and 1 if it fails""" - logname = config.logfile + grepfile = config.grepfile cmd = config.cmd os.chdir(regressionDir) # print(" run_test_case invoking %s" % cmd) os.system(cmd) - if search_log_for_text(config.grepstr, logname): + if search_log_for_text(config.grepstr, grepfile): print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name)) return 0 else: print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name)) - print(" Check %s" % logname) + print(" Check %s" % grepfile) return 1 ################################## @@ -275,7 +275,7 @@ if (nightly): nightMode = "--nightly"; sims = ["questa", "verilator", "vcs"] else: - nightMode = ""; + nightMode = "" sims = [defaultsim] if (coverage): # only run RV64GC tests in coverage mode @@ -291,7 +291,7 @@ configs = [ variant="all", cmd="lint-wally " + nightMode + " | tee " + WALLY + "/sim/questa/logs/all_lints.log", grepstr="lints run with no errors or warnings", - logfile = WALLY + "/sim/questa/logs/all_lints.log") + grepfile = WALLY + "/sim/questa/logs/all_lints.log") ] if (buildroot): @@ -321,13 +321,13 @@ if (testfloat): if ("f_" in config): tests.remove("cvtfp") for test in tests: - sim_log = WALLY + "/sim/questa/logs/"+config+"_"+test+".log" + sim_log = WALLY + "/sim/questa/logs/"+config+"_"+test+".log" # TODO: Change hardcoded questa log directory to simulator tc = TestCase( name=test, variant=config, cmd="wsim --tb testbench_fp " + config + " " + test + " > " + sim_log, grepstr="All Tests completed with 0 errors", - logfile = sim_log) + grepfile = sim_log) configs.append(tc) @@ -372,7 +372,7 @@ if (testfloat): variant=config, cmd="wsim --tb testbench_fp --sim questa " + config + " " + test + " > " + sim_log, grepstr="All Tests completed with 0 errors", - logfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log") + grepfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log") configs.append(tc) From 770d918268ca531d9958569b2053682918a5f4ce Mon Sep 17 00:00:00 2001 From: slmnemo Date: Sat, 20 Apr 2024 16:39:05 -0700 Subject: [PATCH 6/9] Split buildroot and buildrootboot into separate tests to prevent squashing. Removed extraneous comments. --- bin/regression-wally | 40 +++++++++++++++++----------------------- 1 file changed, 17 insertions(+), 23 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index c7f406e25..67aca568b 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -23,7 +23,6 @@ from multiprocessing import Pool, TimeoutError # The element consists of the configuration name, a list of test suites to run, # optionally a string to pass to the simulator, and optionally a nonstandard grep string to check for success -INSTR_LIMIT = 1300000 # multiple of 100000; Set to 0 to run simulation until timeout or Wally Hostname: tests = [ ["rv32e", ["arch32e"]], ["rv32i", ["arch32i"]], @@ -33,15 +32,19 @@ tests = [ "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], # "arch32zcb", "arch32zfad", - ["rv64i", ["arch64i"]], - ["buildroot", ["buildroot"], [f"+INSTR_LIMIT={INSTR_LIMIT}"], str(INSTR_LIMIT)+" instructions"] + ["rv64i", ["arch64i"]] ] # Separate test for full buildroot run +tests_buildrootshort = [ + ["buildroot", ["buildroot"], [f"+INSTR_LIMIT=1400000"], # Instruction limit gets to first OpenSBI UART output + "OpenSBI v", "buildroot_uart.out"] + ] + tests_buildrootboot = [ ["buildroot", ["buildroot"], [f"+INSTR_LIMIT=600000000"], - "WallyHostname login: ", os.environ.get('WALLY')+"/sim/questa/logs/buildroot_uart.out"] + "WallyHostname login: ", "buildroot_uart.out"] ] @@ -221,7 +224,7 @@ def addTests(tests, sim): for t in suites: sim_log = sim_logdir + config + "_" + t + ".log" if (len(test) >= 5): - grepfile = test[4] + grepfile = sim_logdir + test[4] else: grepfile = sim_log tc = TestCase( @@ -294,22 +297,22 @@ configs = [ grepfile = WALLY + "/sim/questa/logs/all_lints.log") ] -if (buildroot): - for sim in sims: - addTests(tests_buildrootboot, sim) - if (coverage): # only run RV64GC tests on Questa in coverage mode addTests(tests64gc_nofp, "questa") if (fp): addTests(tests64gc_fp, "questa") -elif not buildroot: +else: for sim in sims: addTests(tests, sim) addTests(tests64gc_nofp, sim) addTests(tests64gc_fp, sim) + # run derivative configurations in nightly regression - if (nightly): - addTests(derivconfigtests, defaultsim) +if (nightly): + addTests(derivconfigtests, defaultsim) + addTests(tests_buildrootboot, defaultsim) +else: + addTests(tests_buildrootshort, defaultsim) # testfloat tests if (testfloat): @@ -390,26 +393,17 @@ def main(): os.chdir(regressionDir) os.system('./make-tests.sh | tee ./logs/make-tests.log') - if '--all' in sys.argv: - TIMEOUT_DUR = 30*7200 # seconds - #configs.append(getBuildrootTC(boot=True)) - elif '--buildroot' in sys.argv: + if '--buildroot' in sys.argv: TIMEOUT_DUR = 60*7200 # 5 days to run - #configs=[getBuildrootTC(boot=True)] elif '--coverage' in sys.argv: - TIMEOUT_DUR = 20*60 # seconds - # Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage. - # Also it is slow to run. - # configs.append(getBuildrootTC(boot=False)) + TIMEOUT_DUR = 20*60 # seconds os.system('rm -f questa/cov/*.ucdb') elif '--nightly' in sys.argv: TIMEOUT_DUR = 60*1440 # 1 day - #configs.append(getBuildrootTC(boot=False)) elif '--testfloat' in sys.argv: TIMEOUT_DUR = 60*60 # seconds else: TIMEOUT_DUR = 10*60 # seconds - #configs.append(getBuildrootTC(boot=False)) # Scale the number of concurrent processes to the number of test cases, but # max out at a limited number of concurrent processes to not overwhelm the system From 354d4472693c5c4fc2987b91ce0c223e6423ea47 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Sat, 20 Apr 2024 16:56:54 -0700 Subject: [PATCH 7/9] Changed testbench to use fopen instead of opening and closing uartfile whenever writing --- testbench/testbench.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index cf87222c3..28537e4ec 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -256,6 +256,7 @@ module testbench; string signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd; integer begin_signature_addr, end_signature_addr, signature_size; + integer uartoutfile; assign ResetThreshold = 3'd5; @@ -355,8 +356,7 @@ module testbench; memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"}; bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; uartoutfilename = {"logs/", TEST, "_uart.out"}; - rmCmd = {"rm -f ", uartoutfilename}; - unused_int = system(rmCmd); // Delete existing UARToutfile + uartoutfile = $fopen(uartoutfilename, "wb"); end else memfilename = {pathname, tests[test], ".elf.memfile"}; if (riscofTest) begin @@ -383,6 +383,8 @@ module testbench; always @(posedge Validate) // added `endif if(Validate) begin + if (TEST == "buildroot") + $fclose(uartoutfile); if (TEST == "embench") begin // Writes contents of begin_signature to .sim.output file // this contains instret and cycles for start and end of test run, used by embench @@ -602,9 +604,7 @@ module testbench; always @(posedge clk) begin if (TEST == "buildroot") begin if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin - memFile = $fopen(uartoutfilename, "ab"); - $fwrite(memFile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din); - $fclose(memFile); + $fwrite(uartoutfile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din); end end end From 66a002d87906dbdf2e89f466a2ab2fc26f08dc6b Mon Sep 17 00:00:00 2001 From: slmnemo Date: Sat, 20 Apr 2024 16:58:23 -0700 Subject: [PATCH 8/9] Removed unused rmCmd string declaration --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 28537e4ec..958b2734c 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -254,7 +254,7 @@ module testbench; logic ResetCntRst; logic CopyRAM; - string signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd; + string signame, memfilename, bootmemfilename, uartoutfilename, pathname; integer begin_signature_addr, end_signature_addr, signature_size; integer uartoutfile; From f0229e970b92e1bafb8c5c2a3706e74fda6ef2fe Mon Sep 17 00:00:00 2001 From: slmnemo Date: Sat, 20 Apr 2024 17:07:54 -0700 Subject: [PATCH 9/9] Fixed getenvvar verilator bug in rom1p1r, Removed unused system function from testbench. --- src/generic/mem/rom1p1r.sv | 6 ++++++ testbench/testbench.sv | 3 --- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 7a53c529e..5bb82f642 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -26,6 +26,12 @@ // This model actually works correctly with vivado. +`ifdef VERILATOR +import "DPI-C" function string getenvval(input string env_name); +`else +import "DPI-C" function string getenv(input string env_name); +`endif + module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) (input logic clk, input logic ce, diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 958b2734c..b74827165 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -39,7 +39,6 @@ import "DPI-C" function string getenvval(input string env_name); `else import "DPI-C" function string getenv(input string env_name); `endif -import "DPI-C" function int system(input string env_name); module testbench; /* verilator lint_off WIDTHTRUNC */ @@ -329,8 +328,6 @@ module testbench; else assign EcallFaultM = 0; - // this is an unused integer for the return value of `system` - int unused_int; always @(posedge clk) begin //////////////////////////////////////////////////////////////////////////////// // Verify the test ran correctly by checking the memory against a known signature.