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Fixed lint issues.

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This commit is contained in:
Jacob Pease 2024-10-31 15:56:16 -05:00
parent 79fa2c0e63
commit 56a6ad3376
2 changed files with 8 additions and 7 deletions
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5
src/uncore/spi_apb.sv
View File

@ -337,8 +337,9 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
// Receive shift register
always_ff @(posedge PCLK)
if(~PRESETn) ReceiveShiftReg <= 8'b0;
else if (SampleEdge) begin
if(~PRESETn) begin
ReceiveShiftReg <= 8'b0;
end else if (SampleEdge) begin
if (~Transmitting) ReceiveShiftReg <= 8'b0;
else ReceiveShiftReg <= {ReceiveShiftReg[6:0], ShiftIn};
end

10
src/uncore/spi_controller.sv
View File

@ -82,7 +82,7 @@ module spi_controller (
// logic SampleEdge;
// Frame stuff
logic [2:0] BitNum;
logic [3:0] BitNum;
logic LastBit;
//logic EndOfFrame;
//logic EndOfFrameDelay;
@ -158,7 +158,7 @@ module spi_controller (
DivCounter <= 12'b0;
SPICLK <= SckMode[1];
SCK <= 0;
BitNum <= 3'h0;
BitNum <= 4'h0;
PreShiftEdge <= 0;
PreSampleEdge <= 0;
EndOfFrame <= 0;
@ -210,7 +210,7 @@ module spi_controller (
if (SCLKenable | TransmitStart | ResetSCLKenable) begin
DivCounter <= 12'b0;
end else begin
DivCounter = DivCounter + 12'd1;
DivCounter <= DivCounter + 12'd1;
end
// EndOfFrame controller
@ -226,9 +226,9 @@ module spi_controller (
// Increment BitNum
if (ShiftEdge & Transmitting) begin
BitNum <= BitNum + 3'd1;
BitNum <= BitNum + 4'd1;
end else if (EndOfFrameDelay) begin
BitNum <= 3'b0;
BitNum <= 4'b0;
end
end
end