From 56a6ad3376276ece7ca22ae3979346b43d20babf Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 31 Oct 2024 15:56:16 -0500 Subject: [PATCH] Fixed lint issues. --- src/uncore/spi_apb.sv | 5 +++-- src/uncore/spi_controller.sv | 10 +++++----- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv index 911ab3a15..5d3352154 100644 --- a/src/uncore/spi_apb.sv +++ b/src/uncore/spi_apb.sv @@ -337,8 +337,9 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( // Receive shift register always_ff @(posedge PCLK) - if(~PRESETn) ReceiveShiftReg <= 8'b0; - else if (SampleEdge) begin + if(~PRESETn) begin + ReceiveShiftReg <= 8'b0; + end else if (SampleEdge) begin if (~Transmitting) ReceiveShiftReg <= 8'b0; else ReceiveShiftReg <= {ReceiveShiftReg[6:0], ShiftIn}; end diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv index 10ad09f91..605685b4b 100644 --- a/src/uncore/spi_controller.sv +++ b/src/uncore/spi_controller.sv @@ -82,7 +82,7 @@ module spi_controller ( // logic SampleEdge; // Frame stuff - logic [2:0] BitNum; + logic [3:0] BitNum; logic LastBit; //logic EndOfFrame; //logic EndOfFrameDelay; @@ -158,7 +158,7 @@ module spi_controller ( DivCounter <= 12'b0; SPICLK <= SckMode[1]; SCK <= 0; - BitNum <= 3'h0; + BitNum <= 4'h0; PreShiftEdge <= 0; PreSampleEdge <= 0; EndOfFrame <= 0; @@ -210,7 +210,7 @@ module spi_controller ( if (SCLKenable | TransmitStart | ResetSCLKenable) begin DivCounter <= 12'b0; end else begin - DivCounter = DivCounter + 12'd1; + DivCounter <= DivCounter + 12'd1; end // EndOfFrame controller @@ -226,9 +226,9 @@ module spi_controller ( // Increment BitNum if (ShiftEdge & Transmitting) begin - BitNum <= BitNum + 3'd1; + BitNum <= BitNum + 4'd1; end else if (EndOfFrameDelay) begin - BitNum <= 3'b0; + BitNum <= 4'b0; end end end