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Verilator improvements

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This commit is contained in:
David Harris 2023-11-04 03:21:07 -07:00
parent 4de21c206f
commit 568aa3c4a6
3 changed files with 5 additions and 12 deletions
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10
sim/verilate
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@ -8,15 +8,9 @@ basepath=$(dirname $0)/..
#for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
for config in rv64gc; do
echo "$config simulating..."
if !($verilator --timescale "1ns/1ns" --timing --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/wally/cvw.sv $basepath/testbench/common/*.sv $basepath/testbench/testbench.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
if !($verilator --timescale "1ns/1ns" --timing --exe --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
echo "Exiting after $config lint due to errors or warnings"
exit 1
fi
done
echo "All lints run with no errors or warnings"
# --lint-only just runs lint rather than trying to compile and simulate
# -I points to the include directory where files such as `include config.vh are found
# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
# Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.
echo "Verilation complete"

2
testbench/common/shadowmem.sv → testbench/common/DCaacheFlushFSM.sv
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@ -1,5 +1,5 @@
///////////////////////////////////////////
// shadowmem.sv
// DCacheFlushFSM.sv
//
// Written: David Harris David_Harris@hmc.edu and Ross Thompson ross1728@gmail.com
// Modified: 14 June 2023

5
testbench/wallywrapper.sv
View File

@ -1,11 +1,10 @@
///////////////////////////////////////////
// testbench.sv
// wallywrapper.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: Wally Testbench and helper modules
// Applies test programs from the riscv-arch-test and Imperas suites
// Purpose: Wrapper module to define parameters for Wally Verilator linting
//
// A component of the Wally configurable RISC-V project.
//