From 564281b8c1ced00f9382d662a5a9fb793bfa2734 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 22 Aug 2022 16:14:15 +0000
Subject: [PATCH] Removed 2-cycle FPU-IEU latency stall

---
 pipelined/src/ieu/datapath.sv | 1 +
 pipelined/src/ieu/forward.sv  | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv
index df711695e..d6cabb442 100644
--- a/pipelined/src/ieu/datapath.sv
+++ b/pipelined/src/ieu/datapath.sv
@@ -123,6 +123,7 @@ module datapath (
   flopenrc #(`XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW);
   flopenrc #(5)     RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
 
+  // *** simplify WriteDataE in this merge
   // floating point interactions: fcvt, fp stores
   if (`F_SUPPORTED&(`LLEN>`XLEN)) begin:fpmux
     logic [`XLEN-1:0] IFCvtResultW;
diff --git a/pipelined/src/ieu/forward.sv b/pipelined/src/ieu/forward.sv
index ab938b37a..07bd89d3d 100644
--- a/pipelined/src/ieu/forward.sv
+++ b/pipelined/src/ieu/forward.sv
@@ -58,7 +58,7 @@ module forward(
 
   // Stall on dependent operations that finish in Mem Stage and can't bypass in time
   assign MatchDE = (Rs1D == RdE) | (Rs2D == RdE); // Decode-stage instruction source depends on result from execute stage instruction
-  assign FPUStallD = FWriteIntE & MatchDE; 
+  assign FPUStallD = 0; // FWriteIntE & MatchDE; // FPU to Integer transfers have single-cycle latency
   assign LoadStallD = (MemReadE|SCE) & MatchDE;  
   assign MDUStallD = MDUE & MatchDE; 
   assign CSRRdStallD = CSRReadE & MatchDE;