mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
update removal of underscores from kmu
This commit is contained in:
James E. Stine
parent
3b16238a37
commit
55e019c9dd
@ -30,30 +30,29 @@ module packer #(parameter WIDTH=32) (
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input logic [2:0] PackSelect,
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output logic [WIDTH-1:0] PackResult);
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logic [WIDTH/2-1:0] low_half, high_half;
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logic [7:0] low_halfh, high_halfh;
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logic [15:0] low_halfw, high_halfw;
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logic [WIDTH-1:0] Pack;
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logic [WIDTH-1:0] PackH;
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logic [WIDTH-1:0] PackW;
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logic [WIDTH/2-1:0] lowhalf, highhalf;
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logic [7:0] lowhalfh, highhalfh;
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logic [15:0] lowhalfw, highhalfw;
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assign low_half = A[WIDTH/2-1:0];
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assign high_half = B[WIDTH/2-1:0];
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assign low_halfh = A[7:0];
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assign high_halfh = B[7:0];
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assign low_halfw = A[15:0];
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assign high_halfw = B[15:0];
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assign Pack = {high_half, low_half};
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assign PackH = {{(WIDTH-16){1'b0}}, high_halfh, low_halfh};
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assign PackW = {{(WIDTH-32){high_halfw[15]}}, high_halfw, low_halfw};
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always_comb
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begin
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if (PackSelect[1:0] == 2'b11) PackResult = PackH;
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else if (PackSelect[2] == 1'b0) PackResult = Pack;
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else PackResult = PackW;
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end
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logic [WIDTH-1:0] Pack;
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logic [WIDTH-1:0] PackH;
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logic [WIDTH-1:0] PackW;
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assign lowhalf = A[WIDTH/2-1:0];
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assign highhalf = B[WIDTH/2-1:0];
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assign lowhalfh = A[7:0];
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assign highhalfh = B[7:0];
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assign lowhalfw = A[15:0];
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assign highhalfw = B[15:0];
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assign Pack = {highhalf, lowhalf};
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assign PackH = {{(WIDTH-16){1'b0}}, highhalfh, lowhalfh};
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assign PackW = {{(WIDTH-32){highhalfw[15]}}, highhalfw, lowhalfw};
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always_comb
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begin
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if (PackSelect[1:0] == 2'b11) PackResult = PackH;
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else if (PackSelect[2] == 1'b0) PackResult = Pack;
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else PackResult = PackW;
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end
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endmodule
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@ -41,6 +41,5 @@ module zbkb #(parameter WIDTH=32)
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zipper #(WIDTH) zip(.A, .ZipSelect(Funct3[2]), .ZipResult);
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// ZBKB Result Select Mux
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mux3 #(WIDTH) zbkbresultmux(ByteResult, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult);
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mux3 #(WIDTH) zbkbresultmux(ByteResult, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult);
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endmodule
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@ -30,22 +30,21 @@ module zbkx #(parameter WIDTH=32)
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input logic [2:0] ZBKXSelect,
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output logic [WIDTH-1:0] ZBKXResult);
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logic [WIDTH-1:0] xperm_lookup;
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integer i;
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logic [WIDTH-1:0] xpermlookup;
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integer i;
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always_comb begin
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if (ZBKXSelect[0] == 1'b0) begin
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for(i=0; i<WIDTH; i=i+8) begin: xperm8
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xperm_lookup = A >> {B[i+:8], 3'b0};
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ZBKXResult[i+:8] = xperm_lookup[7:0];
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xpermlookup = A >> {B[i+:8], 3'b0};
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ZBKXResult[i+:8] = xpermlookup[7:0];
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end
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end
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else begin
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for(i=0; i<WIDTH; i=i+4) begin: xperm4
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xperm_lookup = A >> {B[i+:4], 2'b0};
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ZBKXResult[i+:4] = xperm_lookup[3:0];
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xpermlookup = A >> {B[i+:4], 2'b0};
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ZBKXResult[i+:4] = xpermlookup[3:0];
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end
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end
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end
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end
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endmodule
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@ -36,12 +36,10 @@ module zipper #(parameter WIDTH=64)
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for (i=0; i<WIDTH/2; i+=1) begin: loop
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assign zip[2*i] = A[i];
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assign zip [2*i+1] = A[i + WIDTH/2];
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assign zip [2*i+1] = A[i + WIDTH/2];
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assign unzip[i] = A[2*i];
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assign unzip[i+WIDTH/2] = A[2*i+1];
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end
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mux2 #(WIDTH) ZipMux(zip, unzip, ZipSelect, ZipResult);
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mux2 #(WIDTH) ZipMux(zip, unzip, ZipSelect, ZipResult);
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endmodule
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// zknd_32.sv
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// zknd32.sv
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//
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// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
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// Created: 27 November 2023
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@ -26,7 +26,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module zknd_32 #(parameter WIDTH=32)
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module zknd32 #(parameter WIDTH=32)
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(input logic [WIDTH-1:0] A, B,
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input logic [6:0] Funct7,
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input logic [2:0] ZKNDSelect,
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@ -36,9 +36,8 @@ module zknd_32 #(parameter WIDTH=32)
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logic [31:0] aes32dsmiRes;
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// RV32
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aes32dsi aes32dsi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32dsiRes));
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aes32dsmi aes32dsmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32dsmiRes));
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aes32dsi aes32dsi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32dsiRes));
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aes32dsmi aes32dsmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32dsmiRes));
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mux2 #(WIDTH) zkndmux (aes32dsiRes, aes32dsmiRes, ZKNDSelect[0], ZKNDResult);
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endmodule
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// zknd_64.sv
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// zknd64.sv
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//
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// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
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// Created: 27 November 2023
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@ -26,7 +26,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module zknd_64 #(parameter WIDTH=32)
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module zknd64 #(parameter WIDTH=32)
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(input logic [WIDTH-1:0] A, B,
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input logic [6:0] Funct7,
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input logic [3:0] RNUM,
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@ -40,12 +40,11 @@ module zknd_64 #(parameter WIDTH=32)
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logic [63:0] aes64ks2Res;
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// RV64
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aes64ds aes64ds (.rs1(A), .rs2(B), .Data_Out(aes64dsRes));
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aes64dsm aes64dsm (.rs1(A), .rs2(B), .Data_Out(aes64dsmRes));
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aes64im aes64im (.rs1(A), .Data_Out(aes64imRes));
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aes64ds aes64ds (.rs1(A), .rs2(B), .DataOut(aes64dsRes));
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aes64dsm aes64dsm (.rs1(A), .rs2(B), .DataOut(aes64dsmRes));
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aes64im aes64im (.rs1(A), .DataOut(aes64imRes));
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aes64ks1i aes64ks1i (.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
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aes64ks2 aes64ks2 (.rs2(B), .rs1(A), .rd(aes64ks2Res));
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mux5 #(WIDTH) zkndmux (aes64dsRes, aes64dsmRes, aes64imRes, aes64ks1iRes, aes64ks2Res, ZKNDSelect, ZKNDResult);
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endmodule
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// zkne_32.sv
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// zkne32.sv
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//
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// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
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// Created: 21 November 2023
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@ -26,7 +26,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module zkne_32 #(parameter WIDTH=32)
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module zkne32 #(parameter WIDTH=32)
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(input logic [WIDTH-1:0] A, B,
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input logic [6:0] Funct7,
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input logic [2:0] ZKNESelect,
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@ -36,9 +36,8 @@ module zkne_32 #(parameter WIDTH=32)
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logic [31:0] aes32esmiRes;
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// RV32
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aes32esi aes32esi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32esiRes));
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aes32esmi aes32esmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32esmiRes));
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aes32esi aes32esi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32esiRes));
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aes32esmi aes32esmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32esmiRes));
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mux2 #(WIDTH) zknemux (aes32esiRes, aes32esmiRes, ZKNESelect[0], ZKNEResult);
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endmodule
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// zkne_64.sv
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// zkne64.sv
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//
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// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
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// Created: 21 November 2023
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@ -26,7 +26,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module zkne_64 #(parameter WIDTH=32)
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module zkne64 #(parameter WIDTH=32)
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(input logic [WIDTH-1:0] A, B,
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input logic [6:0] Funct7,
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input logic [3:0] RNUM,
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@ -39,12 +39,11 @@ module zkne_64 #(parameter WIDTH=32)
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logic [63:0] aes64ks2Res;
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// RV64
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aes64es aes64es (.rs1(A), .rs2(B), .Data_Out(aes64esRes));
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aes64esm aes64esm (.rs1(A), .rs2(B), .Data_Out(aes64esmRes));
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aes64es aes64es (.rs1(A), .rs2(B), .DataOut(aes64esRes));
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aes64esm aes64esm (.rs1(A), .rs2(B), .DataOut(aes64esmRes));
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aes64ks1i aes64ks1i (.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
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aes64ks2 aes64ks2 (.rs2(B), .rs1(A), .rd(aes64ks2Res));
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// 010 is a placeholder to match the select of ZKND's AES64KS1I since they share some instruction
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mux5 #(WIDTH) zknemux (aes64esRes, aes64esmRes, 64'b0, aes64ks1iRes, aes64ks2Res, ZKNESelect, ZKNEResult);
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mux5 #(WIDTH) zknemux (aes64esRes, aes64esmRes, 64'b0, aes64ks1iRes, aes64ks2Res, ZKNESelect, ZKNEResult);
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endmodule
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71
src/ieu/kmu/zknh32.sv
Normal file
71
src/ieu/kmu/zknh32.sv
Normal file
@ -0,0 +1,71 @@
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///////////////////////////////////////////
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// zknh32.sv
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//
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// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
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// Created: 13 February 2024
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//
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// Purpose: RISC-V ZKNH 32-Bit top level unit
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module zknh32 (input logic [31:0] A, B,
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input logic [3:0] ZKNHSelect,
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output logic [31:0] ZKNHResult);
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logic [31:0] sha256sig0res;
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logic [31:0] sha256sig1res;
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logic [31:0] sha256sum0res;
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logic [31:0] sha256sum1res;
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logic [31:0] sha512sig0hres;
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logic [31:0] sha512sig0lres;
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logic [31:0] sha512sig1hres;
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logic [31:0] sha512sig1lres;
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logic [31:0] sha512sum0rres;
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logic [31:0] sha512sum1rres;
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sha256sig0 #(32) sha256sig0(A, sha256sig0res);
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sha256sig1 #(32) sha256sig1(A, sha256sig1res);
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sha256sum0 #(32) sha256sum0(A, sha256sum0res);
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sha256sum1 #(32) sha256sum1(A, sha256sum1res);
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sha512sig0h sha512sig0h(A, B, sha512sig0hres);
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sha512sig0l sha512sig0l(A, B, sha512sig0lres);
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sha512sig1h sha512sig1h(A, B, sha512sig1hres);
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sha512sig1l sha512sig1l(A, B, sha512sig1lres);
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sha512sum0r sha512sum0r(A, B, sha512sum0rres);
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sha512sum1r sha512sum1r(A, B, sha512sum1rres);
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// Result Select Mux
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always_comb begin
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casez(ZKNHSelect)
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4'b0000: ZKNHResult = sha256sig0res;
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4'b0001: ZKNHResult = sha256sig1res;
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4'b0010: ZKNHResult = sha256sum0res;
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4'b0011: ZKNHResult = sha256sum1res;
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4'b0100: ZKNHResult = sha512sig0hres;
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4'b0101: ZKNHResult = sha512sig0lres;
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4'b0110: ZKNHResult = sha512sig1hres;
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4'b0111: ZKNHResult = sha512sig1lres;
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4'b1000: ZKNHResult = sha512sum0rres;
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4'b1001: ZKNHResult = sha512sum1rres;
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default ZKNHResult = 0;
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endcase
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end
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endmodule
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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// zknh_64.sv
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// zknh64.sv
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//
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// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
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// Created: 13 February 2024
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@ -25,41 +25,40 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module zknh_64 (input logic [63:0] A, B, input logic [3:0] ZKNHSelect,
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output logic [63:0] ZKNHResult);
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module zknh64 (input logic [63:0] A, B, input logic [3:0] ZKNHSelect,
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output logic [63:0] ZKNHResult);
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logic [63:0] sha256sig0_res;
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logic [63:0] sha256sig1_res;
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logic [63:0] sha256sum0_res;
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logic [63:0] sha256sum1_res;
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logic [63:0] sha256sig0res;
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logic [63:0] sha256sig1res;
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logic [63:0] sha256sum0res;
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logic [63:0] sha256sum1res;
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logic [63:0] sha512sig0_res;
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logic [63:0] sha512sig1_res;
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logic [63:0] sha512sum0_res;
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logic [63:0] sha512sum1_res;
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logic [63:0] sha512sig0res;
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logic [63:0] sha512sig1res;
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logic [63:0] sha512sum0res;
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logic [63:0] sha512sum1res;
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sha256sig0 #(64) sha256sig0(A, sha256sig0_res);
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sha256sig1 #(64) sha256sig1(A, sha256sig1_res);
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sha256sum0 #(64) sha256sum0(A, sha256sum0_res);
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sha256sum1 #(64) sha256sum1(A, sha256sum1_res);
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sha512sig0 sha512sig0(A, sha512sig0_res);
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sha512sig1 sha512sig1(A, sha512sig1_res);
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sha512sum0 sha512sum0(A, sha512sum0_res);
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sha512sum1 sha512sum1(A, sha512sum1_res);
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sha256sig0 #(64) sha256sig0(A, sha256sig0res);
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sha256sig1 #(64) sha256sig1(A, sha256sig1res);
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sha256sum0 #(64) sha256sum0(A, sha256sum0res);
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sha256sum1 #(64) sha256sum1(A, sha256sum1res);
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sha512sig0 sha512sig0(A, sha512sig0res);
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sha512sig1 sha512sig1(A, sha512sig1res);
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sha512sum0 sha512sum0(A, sha512sum0res);
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sha512sum1 sha512sum1(A, sha512sum1res);
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// Result Select Mux
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always_comb begin
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casez(ZKNHSelect)
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4'b0000: ZKNHResult = sha256sig0_res;
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4'b0001: ZKNHResult = sha256sig1_res;
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4'b0010: ZKNHResult = sha256sum0_res;
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4'b0011: ZKNHResult = sha256sum1_res;
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4'b1010: ZKNHResult = sha512sig0_res;
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4'b1011: ZKNHResult = sha512sig1_res;
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4'b1100: ZKNHResult = sha512sum0_res;
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4'b1101: ZKNHResult = sha512sum1_res;
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4'b0000: ZKNHResult = sha256sig0res;
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4'b0001: ZKNHResult = sha256sig1res;
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4'b0010: ZKNHResult = sha256sum0res;
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4'b0011: ZKNHResult = sha256sum1res;
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4'b1010: ZKNHResult = sha512sig0res;
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4'b1011: ZKNHResult = sha512sig1res;
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4'b1100: ZKNHResult = sha512sum0res;
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4'b1101: ZKNHResult = sha512sum1res;
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default ZKNHResult = 0;
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endcase
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end
|
||||
|
||||
endmodule
|
||||
@ -1,72 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// zknh_32.sv
|
||||
//
|
||||
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
|
||||
// Created: 13 February 2024
|
||||
//
|
||||
// Purpose: RISC-V ZKNH 32-Bit top level unit
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
// https://github.com/openhwgroup/cvw
|
||||
//
|
||||
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module zknh_32 (input logic [31:0] A, B,
|
||||
input logic [3:0] ZKNHSelect,
|
||||
output logic [31:0] ZKNHResult);
|
||||
|
||||
logic [31:0] sha256sig0_res;
|
||||
logic [31:0] sha256sig1_res;
|
||||
logic [31:0] sha256sum0_res;
|
||||
logic [31:0] sha256sum1_res;
|
||||
|
||||
logic [31:0] sha512sig0h_res;
|
||||
logic [31:0] sha512sig0l_res;
|
||||
logic [31:0] sha512sig1h_res;
|
||||
logic [31:0] sha512sig1l_res;
|
||||
logic [31:0] sha512sum0r_res;
|
||||
logic [31:0] sha512sum1r_res;
|
||||
|
||||
sha256sig0 #(32) sha256sig0(A, sha256sig0_res);
|
||||
sha256sig1 #(32) sha256sig1(A, sha256sig1_res);
|
||||
sha256sum0 #(32) sha256sum0(A, sha256sum0_res);
|
||||
sha256sum1 #(32) sha256sum1(A, sha256sum1_res);
|
||||
sha512sig0h sha512sig0h(A, B, sha512sig0h_res);
|
||||
sha512sig0l sha512sig0l(A, B, sha512sig0l_res);
|
||||
sha512sig1h sha512sig1h(A, B, sha512sig1h_res);
|
||||
sha512sig1l sha512sig1l(A, B, sha512sig1l_res);
|
||||
sha512sum0r sha512sum0r(A, B, sha512sum0r_res);
|
||||
sha512sum1r sha512sum1r(A, B, sha512sum1r_res);
|
||||
|
||||
// Result Select Mux
|
||||
always_comb begin
|
||||
casez(ZKNHSelect)
|
||||
4'b0000: ZKNHResult = sha256sig0_res;
|
||||
4'b0001: ZKNHResult = sha256sig1_res;
|
||||
4'b0010: ZKNHResult = sha256sum0_res;
|
||||
4'b0011: ZKNHResult = sha256sum1_res;
|
||||
4'b0100: ZKNHResult = sha512sig0h_res;
|
||||
4'b0101: ZKNHResult = sha512sig0l_res;
|
||||
4'b0110: ZKNHResult = sha512sig1h_res;
|
||||
4'b0111: ZKNHResult = sha512sig1l_res;
|
||||
4'b1000: ZKNHResult = sha512sum0r_res;
|
||||
4'b1001: ZKNHResult = sha512sum1r_res;
|
||||
default ZKNHResult = 0;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue
Block a user