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Removing debug signals

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Huda-10xe 2024-12-03 04:10:22 -08:00
parent ffdaca2760
commit 54e09df77c
1 changed files with 2 additions and 2 deletions
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4
testbench/common/wallyTracer.sv
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@ -122,8 +122,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE;
assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN;
assign PageType_iM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal; assign PageType_iM = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal;
assign PageType_dM = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal; assign PageType_dM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal;
logic valid; logic valid;