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Starting to adust number of cycles for division/sqrt

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David Harris 2022-09-17 05:58:59 -07:00
parent f07d4b3481
commit 54ad15d595
1 changed files with 4 additions and 1 deletions
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pipelined/src/fpu/fdivsqrtfsm.sv
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@ -52,17 +52,20 @@ module fdivsqrtfsm(
logic [`DURLEN-1:0] step; logic [`DURLEN-1:0] step;
logic SpecialCase; logic SpecialCase;
logic [`DURLEN-1:0] cycles;
assign EarlyTermShiftE = step; assign EarlyTermShiftE = step;
// terminate immediately on special cases // terminate immediately on special cases
assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE); assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
assign cycles = (`DURLEN)'((`DIVN+2+(`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES)+(`RADIX/4));
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (reset) begin if (reset) begin
state <= #1 IDLE; state <= #1 IDLE;
end else if (DivStart&~StallE) begin end else if (DivStart&~StallE) begin
step <= (`DURLEN)'(`FPDUR); // *** this should be adjusted to depend on the precision; sqrt should use one fewer step becasue firststep=1 step <= cycles; // *** this should be adjusted to depend on the precision; sqrt should use one fewer step becasue firststep=1
if (SpecialCase) state <= #1 DONE; if (SpecialCase) state <= #1 DONE;
else state <= #1 BUSY; else state <= #1 BUSY;
end else if (DivDone) begin end else if (DivDone) begin