From 54ad15d5957e2f6d04b52570ac4705401e388ee1 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 17 Sep 2022 05:58:59 -0700
Subject: [PATCH] Starting to adust number of cycles for division/sqrt

---
 pipelined/src/fpu/fdivsqrtfsm.sv | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/pipelined/src/fpu/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrtfsm.sv
index 3e4bd2f2d..959474dda 100644
--- a/pipelined/src/fpu/fdivsqrtfsm.sv
+++ b/pipelined/src/fpu/fdivsqrtfsm.sv
@@ -52,17 +52,20 @@ module fdivsqrtfsm(
 
   logic [`DURLEN-1:0] step;
   logic SpecialCase;
+  logic [`DURLEN-1:0] cycles;
 
   assign EarlyTermShiftE = step;
 
   // terminate immediately on special cases
   assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
 
+  assign cycles = (`DURLEN)'((`DIVN+2+(`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES)+(`RADIX/4));
+
   always_ff @(posedge clk) begin
       if (reset) begin
           state <= #1 IDLE; 
       end else if (DivStart&~StallE) begin 
-          step <= (`DURLEN)'(`FPDUR); // *** this should be adjusted to depend on the precision; sqrt should use one fewer step becasue firststep=1
+          step <= cycles; // *** this should be adjusted to depend on the precision; sqrt should use one fewer step becasue firststep=1
           if (SpecialCase) state <= #1 DONE;
           else             state <= #1 BUSY;
       end else if (DivDone) begin