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https://github.com/openhwgroup/cvw
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Moved all remaining bus logic from the LSU into ahbcacheinterface.
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c028306ba3
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@ -40,16 +40,21 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
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// bus interface
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// bus interface
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input logic HREADY,
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input logic HREADY,
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input logic [`XLEN-1:0] HRDATA,
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input logic [`AHBW-1:0] HRDATA,
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output logic [2:0] HSIZE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [2:0] HBURST,
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output logic [1:0] HTRANS,
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output logic [1:0] HTRANS,
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output logic HWRITE,
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output logic HWRITE,
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output logic [`PA_BITS-1:0] HADDR,
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output logic [`PA_BITS-1:0] HADDR,
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output logic [`AHBW-1:0] HWDATA,
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output logic [`AHBW/8-1:0] HWSTRB,
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output logic [LOGWPL-1:0] BeatCount,
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output logic [LOGWPL-1:0] BeatCount,
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// cache interface
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// cache interface
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input logic [`PA_BITS-1:0] CacheBusAdr,
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input logic [`PA_BITS-1:0] CacheBusAdr,
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input logic [`LLEN-1:0] CacheReadDataWordM,
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input logic [`LLEN-1:0] WriteDataM,
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input logic CacheableOrFlushCacheM,
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input logic [1:0] CacheBusRW,
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input logic [1:0] CacheBusRW,
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output logic CacheBusAck,
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output logic CacheBusAck,
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output logic [LINELEN-1:0] FetchBuffer,
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output logic [LINELEN-1:0] FetchBuffer,
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@ -65,23 +70,48 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
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output logic BusStall,
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output logic BusStall,
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output logic BusCommitted);
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output logic BusCommitted);
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localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // *** fix me duplciated in lsu.
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localparam integer BeatCountThreshold = CACHE_ENABLED ? BEATSPERLINE - 1 : 0;
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localparam integer BeatCountThreshold = CACHE_ENABLED ? BEATSPERLINE - 1 : 0;
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logic [`PA_BITS-1:0] LocalHADDR;
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logic [`PA_BITS-1:0] LocalHADDR;
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logic [LOGWPL-1:0] BeatCountDelayed;
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logic [LOGWPL-1:0] BeatCountDelayed;
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logic CaptureEn;
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logic CaptureEn;
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logic [`AHBW-1:0] PreHWDATA;
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genvar index;
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genvar index;
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for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer
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for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer
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logic [BEATSPERLINE-1:0] CaptureBeat;
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logic [BEATSPERLINE-1:0] CaptureBeat;
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assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed);
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assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed);
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flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA),
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flopen #(`AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA),
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.q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN]));
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.q(FetchBuffer[(index+1)*`AHBW-1:index*`AHBW]));
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end
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end
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mux2 #(`PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR);
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mux2 #(`PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR);
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assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, BeatCount} << $clog2(`XLEN/8)) + LocalHADDR;
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assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, BeatCount} << $clog2(`AHBW/8)) + LocalHADDR;
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mux2 #(3) sizemux(.d0(Funct3), .d1(`XLEN == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE));
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mux2 #(3) sizemux(.d0(Funct3), .d1(`AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE));
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// When AHBW is less than LLEN need extra muxes to select the subword from cache's read data.
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logic [`AHBW-1:0] CacheReadDataWordAHB;
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if(LLENPOVERAHBW > 1) begin
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logic [`AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0];
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genvar index;
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for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux
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assign AHBWordSets[index] = CacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)];
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end
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assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]];
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end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0];
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mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]),
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.s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
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flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
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// *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
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// probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
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logic [`AHBW/8-1:0] BusByteMaskM;
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swbytemask #(`AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(`AHBW/8)-1:0]), .ByteMask(BusByteMaskM));
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flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB);
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buscachefsm #(BeatCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
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buscachefsm #(BeatCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
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.HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
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.HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
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@ -238,10 +238,10 @@ module ifu (
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ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
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ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
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ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
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ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
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.HRDATA,
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.HRDATA,
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.Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS),
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.Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
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.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
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.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
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.BeatCount(), .Cacheable(CacheableF), .SelBusBeat(),
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.BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0),
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.CacheBusAck(ICacheBusAck),
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.CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
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.FetchBuffer, .PAdr(PCPF),
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.FetchBuffer, .PAdr(PCPF),
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.BusRW, .CPUBusy,
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.BusRW, .CPUBusy,
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.BusStall, .BusCommitted(BusCommittedF));
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.BusStall, .BusCommitted(BusCommittedF));
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@ -233,7 +233,6 @@ module lsu (
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logic [AHBWLOGBWPL-1:0] BeatCount;
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logic [AHBWLOGBWPL-1:0] BeatCount;
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logic DCacheBusAck;
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logic DCacheBusAck;
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logic SelBusBeat;
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logic SelBusBeat;
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logic [`XLEN-1:0] PreHWDATA; //*** change name
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logic [`XLEN/8-1:0] ByteMaskMDelay;
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logic [`XLEN/8-1:0] ByteMaskMDelay;
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logic [1:0] CacheBusRW, BusRW;
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logic [1:0] CacheBusRW, BusRW;
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localparam integer LLENPOVERAHBW = `LLEN / `AHBW;
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localparam integer LLENPOVERAHBW = `LLEN / `AHBW;
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@ -260,10 +259,10 @@ module lsu (
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.CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
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.CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
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ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface(
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ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface(
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.HCLK(clk), .HRESETn(~reset), .Flush(FlushW),
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.HCLK(clk), .HRESETn(~reset), .Flush(FlushW),
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.HRDATA,
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.HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
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.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
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.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
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.BeatCount, .SelBusBeat,
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.BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM), .WriteDataM(LSUWriteDataM),
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.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW,
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.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .CacheableOrFlushCacheM,
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.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM),
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.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM),
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.Cacheable(CacheableOrFlushCacheM), .BusRW, .CPUBusy,
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.Cacheable(CacheableOrFlushCacheM), .BusRW, .CPUBusy,
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.BusStall, .BusCommitted(BusCommittedM));
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.BusStall, .BusCommitted(BusCommittedM));
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@ -275,29 +274,6 @@ module lsu (
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mux3 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({LLENPOVERAHBW{FetchBuffer[`XLEN-1:0]}}),
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mux3 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({LLENPOVERAHBW{FetchBuffer[`XLEN-1:0]}}),
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.d2({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}),
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.d2({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}),
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.s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM));
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.s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM));
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// When AHBW is less than LLEN need extra muxes to select the subword from cache's read data.
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logic [`AHBW-1:0] DCacheReadDataWordAHB;
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if(LLENPOVERAHBW > 1) begin
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logic [`AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0];
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genvar index;
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for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux
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assign AHBWordSets[index] = DCacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)];
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end
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assign DCacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]];
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end else assign DCacheReadDataWordAHB = DCacheReadDataWordM[`AHBW-1:0];
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mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordAHB), .d1(LSUWriteDataM[`AHBW-1:0]),
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.s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
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flopen #(`AHBW) wdreg(clk, LSUHREADY, PreHWDATA, LSUHWDATA); // delay HWDATA by 1 cycle per spec
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// *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
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// probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
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logic [`AHBW/8-1:0] BusByteMaskM;
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swbytemask #(`AHBW) busswbytemask(.Size(LSUHSIZE), .Adr(PAdrM[$clog2(`AHBW/8)-1:0]), .ByteMask(BusByteMaskM));
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flop #(`AHBW/8) HWSTRBReg(clk, BusByteMaskM[`AHBW/8-1:0], LSUHWSTRB);
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end else begin : passthrough // just needs a register to hold the value from the bus
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end else begin : passthrough // just needs a register to hold the value from the bus
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logic CaptureEn;
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logic CaptureEn;
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logic [1:0] BusRW;
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logic [1:0] BusRW;
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