From 54544ae251a16f527797192070fb16851f98de26 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Nov 2022 14:30:32 -0600 Subject: [PATCH] Moved all remaining bus logic from the LSU into ahbcacheinterface. --- pipelined/src/ebu/ahbcacheinterface.sv | 40 ++++++++++++++++++++++---- pipelined/src/ifu/ifu.sv | 6 ++-- pipelined/src/lsu/lsu.sv | 30 ++----------------- 3 files changed, 41 insertions(+), 35 deletions(-) diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index 9b7b8f4bf..530cdb42c 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -40,16 +40,21 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE // bus interface input logic HREADY, - input logic [`XLEN-1:0] HRDATA, + input logic [`AHBW-1:0] HRDATA, output logic [2:0] HSIZE, output logic [2:0] HBURST, output logic [1:0] HTRANS, output logic HWRITE, output logic [`PA_BITS-1:0] HADDR, + output logic [`AHBW-1:0] HWDATA, + output logic [`AHBW/8-1:0] HWSTRB, output logic [LOGWPL-1:0] BeatCount, // cache interface input logic [`PA_BITS-1:0] CacheBusAdr, + input logic [`LLEN-1:0] CacheReadDataWordM, + input logic [`LLEN-1:0] WriteDataM, + input logic CacheableOrFlushCacheM, input logic [1:0] CacheBusRW, output logic CacheBusAck, output logic [LINELEN-1:0] FetchBuffer, @@ -65,23 +70,48 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE output logic BusStall, output logic BusCommitted); + localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // *** fix me duplciated in lsu. + localparam integer BeatCountThreshold = CACHE_ENABLED ? BEATSPERLINE - 1 : 0; logic [`PA_BITS-1:0] LocalHADDR; logic [LOGWPL-1:0] BeatCountDelayed; logic CaptureEn; + logic [`AHBW-1:0] PreHWDATA; genvar index; for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer logic [BEATSPERLINE-1:0] CaptureBeat; assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed); - flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), - .q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN])); + flopen #(`AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), + .q(FetchBuffer[(index+1)*`AHBW-1:index*`AHBW])); end mux2 #(`PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR); - assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, BeatCount} << $clog2(`XLEN/8)) + LocalHADDR; + assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, BeatCount} << $clog2(`AHBW/8)) + LocalHADDR; - mux2 #(3) sizemux(.d0(Funct3), .d1(`XLEN == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE)); + mux2 #(3) sizemux(.d0(Funct3), .d1(`AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE)); + + // When AHBW is less than LLEN need extra muxes to select the subword from cache's read data. + logic [`AHBW-1:0] CacheReadDataWordAHB; + if(LLENPOVERAHBW > 1) begin + logic [`AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; + genvar index; + for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux + assign AHBWordSets[index] = CacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)]; + end + assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]]; + end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0]; + mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]), + .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); + flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec + + // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. + // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0. + logic [`AHBW/8-1:0] BusByteMaskM; + swbytemask #(`AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(`AHBW/8)-1:0]), .ByteMask(BusByteMaskM)); + + flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB); + buscachefsm #(BeatCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 415784377..0798d25f5 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -238,10 +238,10 @@ module ifu ( ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), .HRDATA, - .Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), + .Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr), - .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), - .CacheBusAck(ICacheBusAck), + .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0), + .CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0), .FetchBuffer, .PAdr(PCPF), .BusRW, .CPUBusy, .BusStall, .BusCommitted(BusCommittedF)); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index e66fb35a6..6ac9bf4f2 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -233,7 +233,6 @@ module lsu ( logic [AHBWLOGBWPL-1:0] BeatCount; logic DCacheBusAck; logic SelBusBeat; - logic [`XLEN-1:0] PreHWDATA; //*** change name logic [`XLEN/8-1:0] ByteMaskMDelay; logic [1:0] CacheBusRW, BusRW; localparam integer LLENPOVERAHBW = `LLEN / `AHBW; @@ -260,10 +259,10 @@ module lsu ( .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .Flush(FlushW), - .HRDATA, + .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), - .BeatCount, .SelBusBeat, - .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, + .BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM), .WriteDataM(LSUWriteDataM), + .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .CacheableOrFlushCacheM, .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM), .Cacheable(CacheableOrFlushCacheM), .BusRW, .CPUBusy, .BusStall, .BusCommitted(BusCommittedM)); @@ -275,29 +274,6 @@ module lsu ( mux3 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({LLENPOVERAHBW{FetchBuffer[`XLEN-1:0]}}), .d2({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}), .s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM)); - - // When AHBW is less than LLEN need extra muxes to select the subword from cache's read data. - logic [`AHBW-1:0] DCacheReadDataWordAHB; - if(LLENPOVERAHBW > 1) begin - logic [`AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; - genvar index; - for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux - assign AHBWordSets[index] = DCacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)]; - end - assign DCacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]]; - end else assign DCacheReadDataWordAHB = DCacheReadDataWordM[`AHBW-1:0]; - mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordAHB), .d1(LSUWriteDataM[`AHBW-1:0]), - .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); - - flopen #(`AHBW) wdreg(clk, LSUHREADY, PreHWDATA, LSUHWDATA); // delay HWDATA by 1 cycle per spec - - // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. - // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0. - logic [`AHBW/8-1:0] BusByteMaskM; - swbytemask #(`AHBW) busswbytemask(.Size(LSUHSIZE), .Adr(PAdrM[$clog2(`AHBW/8)-1:0]), .ByteMask(BusByteMaskM)); - - flop #(`AHBW/8) HWSTRBReg(clk, BusByteMaskM[`AHBW/8-1:0], LSUHWSTRB); - end else begin : passthrough // just needs a register to hold the value from the bus logic CaptureEn; logic [1:0] BusRW;