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More btb cleanup.

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This commit is contained in:
Ross Thompson 2023-01-25 12:14:18 -06:00
parent 62d812b150
commit 541524a754
2 changed files with 9 additions and 9 deletions
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10
pipelined/src/ifu/brpred/bpred.sv
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@ -60,7 +60,7 @@ module bpred (
output logic PredictionInstrClassWrongM // Class prediction is wrong output logic PredictionInstrClassWrongM // Class prediction is wrong
); );
logic BTBValidF; logic PredValidF;
logic [1:0] DirPredictionF; logic [1:0] DirPredictionF;
logic [3:0] PredInstrClassF, PredInstrClassD, PredInstrClassE; logic [3:0] PredInstrClassF, PredInstrClassD, PredInstrClassE;
@ -128,9 +128,9 @@ module bpred (
// 1) A direction (1 = Taken, 0 = Not Taken) // 1) A direction (1 = Taken, 0 = Not Taken)
// 2) Any information which is necessary for the predictor to build its next state. // 2) Any information which is necessary for the predictor to build its next state.
// For a 2 bit table this is the prediction count. // For a 2 bit table this is the prediction count.
assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & BTBValidF) | assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) |
PredInstrClassF[2] | PredInstrClassF[2] |
(PredInstrClassF[1] & BTBValidF) ; (PredInstrClassF[1] & PredValidF) ;
// Part 2 Branch target address prediction // Part 2 Branch target address prediction
// *** For now the BTB will house the direct and indirect targets // *** For now the BTB will house the direct and indirect targets
@ -140,8 +140,8 @@ module bpred (
.*, // Stalls and flushes .*, // Stalls and flushes
.PCNextF, .PCNextF,
.BTBPredPCF, .BTBPredPCF,
.InstrClass(PredInstrClassF), .PredInstrClassF,
.Valid(BTBValidF), .PredValidF,
// update // update
.UpdateEN(|InstrClassE | PredictionInstrClassWrongE), .UpdateEN(|InstrClassE | PredictionInstrClassWrongE),
.PCE, .PCE,

8
pipelined/src/ifu/brpred/btb.sv
View File

@ -38,8 +38,8 @@ module btb
input logic StallF, StallE, StallM, FlushM, input logic StallF, StallE, StallM, FlushM,
input logic [`XLEN-1:0] PCNextF, input logic [`XLEN-1:0] PCNextF,
output logic [`XLEN-1:0] BTBPredPCF, output logic [`XLEN-1:0] BTBPredPCF,
output logic [3:0] InstrClass, output logic [3:0] PredInstrClassF,
output logic Valid, output logic PredValidF,
// update // update
input logic UpdateEN, input logic UpdateEN,
input logic [`XLEN-1:0] PCE, input logic [`XLEN-1:0] PCE,
@ -72,13 +72,13 @@ module btb
end else if (UpdateEN & ~StallM & ~FlushM) begin end else if (UpdateEN & ~StallM & ~FlushM) begin
ValidBits[PCEIndex] <= #1 ~ UpdateInvalid; ValidBits[PCEIndex] <= #1 ~ UpdateInvalid;
end end
Valid = ValidBits[PCNextFIndex]; PredValidF = ValidBits[PCNextFIndex];
end end
// An optimization may be using a PC relative address. // An optimization may be using a PC relative address.
// *** need to add forwarding. // *** need to add forwarding.
ram2p1r1wbe #(2**Depth, `XLEN+4) memory( ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
.clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}), .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({PredInstrClassF, BTBPredPCF}),
.ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1));
endmodule endmodule