diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index 6817dfd59..dd7b9e850 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -60,7 +60,7 @@ module bpred (
    output logic             PredictionInstrClassWrongM // Class prediction is wrong
    );
 
-  logic                     BTBValidF;
+  logic                     PredValidF;
   logic [1:0]               DirPredictionF;
 
   logic [3:0]               PredInstrClassF, PredInstrClassD, PredInstrClassE;
@@ -128,9 +128,9 @@ module bpred (
   // 1) A direction (1 = Taken, 0 = Not Taken)
   // 2) Any information which is necessary for the predictor to build its next state.
   // For a 2 bit table this is the prediction count.
-  assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & BTBValidF) | 
+  assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
          PredInstrClassF[2] |
-         (PredInstrClassF[1] & BTBValidF) ;
+         (PredInstrClassF[1] & PredValidF) ;
 
   // Part 2 Branch target address prediction
   // *** For now the BTB will house the direct and indirect targets
@@ -140,8 +140,8 @@ module bpred (
           .*, // Stalls and flushes
           .PCNextF,
           .BTBPredPCF,
-          .InstrClass(PredInstrClassF),
-          .Valid(BTBValidF),
+          .PredInstrClassF,
+          .PredValidF,
           // update
           .UpdateEN(|InstrClassE | PredictionInstrClassWrongE),
           .PCE,
diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv
index 8eba026ec..839b1b7d5 100644
--- a/pipelined/src/ifu/brpred/btb.sv
+++ b/pipelined/src/ifu/brpred/btb.sv
@@ -38,8 +38,8 @@ module btb
    input  logic             StallF, StallE, StallM, FlushM,
    input  logic [`XLEN-1:0] PCNextF,
    output logic [`XLEN-1:0] BTBPredPCF,
-   output logic [3:0]       InstrClass,
-   output logic             Valid,
+   output logic [3:0]       PredInstrClassF,
+   output logic             PredValidF,
    // update
    input  logic             UpdateEN,
    input  logic [`XLEN-1:0] PCE,
@@ -72,13 +72,13 @@ module btb
     end else if (UpdateEN & ~StallM & ~FlushM) begin
       ValidBits[PCEIndex] <= #1 ~ UpdateInvalid;
     end
-	Valid = ValidBits[PCNextFIndex];
+	PredValidF = ValidBits[PCNextFIndex];
   end
 
   // An optimization may be using a PC relative address.
   // *** need to add forwarding.
   ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
-    .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}),
+    .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({PredInstrClassF, BTBPredPCF}),
      .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1));
 
 endmodule