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removed duplicate synth scripts

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This commit is contained in:
Kevin Kim 2023-08-29 08:25:31 -07:00
parent 098111ea85
commit 53fc6e1ca7
2 changed files with 12 additions and 7 deletions
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7
synthDC/Makefile
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@ -2,7 +2,7 @@
# Makefile for synthesis # Makefile for synthesis
# Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 # Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022
# Madeleine Masser-Frye (mmasserfrye@hmc.edu) 1/27/2023 # Madeleine Masser-Frye (mmasserfrye@hmc.edu) 1/27/2023
NAME := synth
# defaults # defaults
export DESIGN ?= wallypipelinedcore export DESIGN ?= wallypipelinedcore
export FREQ ?= 10000 export FREQ ?= 10000
@ -23,11 +23,6 @@ export DRIVE ?= FLOP
export USESRAM ?= 0 export USESRAM ?= 0
export WRAPPER ?= 0 export WRAPPER ?= 0
ifeq ($(WRAPPER),1)
NAME := synthWrapper
else
NAME := synth
endif
time := $(shell date +%F-%H-%M) time := $(shell date +%F-%H-%M)
hash := $(shell git rev-parse --short HEAD) hash := $(shell git rev-parse --short HEAD)

10
synthDC/scripts/synth.tcl
View File

@ -16,6 +16,7 @@ suppress_message {VER-173}
# Enable Multicore # Enable Multicore
set_host_options -max_cores $::env(MAXCORES) set_host_options -max_cores $::env(MAXCORES)
# get outputDir and configDir from environment (Makefile) # get outputDir and configDir from environment (Makefile)
set outputDir $::env(OUTPUTDIR) set outputDir $::env(OUTPUTDIR)
set cfg $::env(CONFIGDIR) set cfg $::env(CONFIGDIR)
@ -23,12 +24,17 @@ set hdl_src "../src"
set saifpower $::env(SAIFPOWER) set saifpower $::env(SAIFPOWER)
set maxopt $::env(MAXOPT) set maxopt $::env(MAXOPT)
set drive $::env(DRIVE) set drive $::env(DRIVE)
set wrapper $::env(WRAPPER)
eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/} eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/}
#eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/} #eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
if {$wrapper ==1 } {
eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/}
}
# Only for FMA class project; comment out when done # Only for FMA class project; comment out when done
# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/} # eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
@ -42,7 +48,11 @@ if { $saifpower == 1 } {
set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv] set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv]
# Set toplevel # Set toplevel
if { $wrapper == 1 } {
set my_toplevel $::env(DESIGN)wrapper
} else {
set my_toplevel $::env(DESIGN) set my_toplevel $::env(DESIGN)
}
# Set number of significant digits # Set number of significant digits
set report_default_significant_digits 6 set report_default_significant_digits 6