From 53fc6e1ca7a69f90b4618518c6f9193ef1763c44 Mon Sep 17 00:00:00 2001
From: Kevin Kim <kevindkim723@gmail.com>
Date: Tue, 29 Aug 2023 08:25:31 -0700
Subject: [PATCH] removed duplicate synth scripts

---
 synthDC/Makefile          |  7 +------
 synthDC/scripts/synth.tcl | 12 +++++++++++-
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index 44b938d34..57b478795 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -2,7 +2,7 @@
 # Makefile for synthesis
 # Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022
 # Madeleine Masser-Frye (mmasserfrye@hmc.edu) 1/27/2023
-
+NAME := synth
 # defaults
 export DESIGN ?= wallypipelinedcore
 export FREQ ?= 10000
@@ -23,11 +23,6 @@ export DRIVE ?= FLOP
 export USESRAM ?= 0
 export WRAPPER ?= 0
 
-ifeq ($(WRAPPER),1)
-	NAME := synthWrapper
-else 
-	NAME := synth
-endif
 
 time := $(shell date +%F-%H-%M)
 hash := $(shell git rev-parse --short HEAD)
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 7de696da2..075bb5db9 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -16,6 +16,7 @@ suppress_message {VER-173}
 # Enable Multicore
 set_host_options -max_cores $::env(MAXCORES)
 
+
 # get outputDir and configDir from environment (Makefile)
 set outputDir $::env(OUTPUTDIR)
 set cfg $::env(CONFIGDIR)
@@ -23,12 +24,17 @@ set hdl_src "../src"
 set saifpower $::env(SAIFPOWER)
 set maxopt $::env(MAXOPT)
 set drive $::env(DRIVE)
+set wrapper $::env(WRAPPER)
 
 eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/}
 #eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
+if {$wrapper ==1 } {
+    eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/}
+}
+
 
 # Only for FMA class project; comment out when done
 # eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
@@ -42,7 +48,11 @@ if { $saifpower == 1 } {
 set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv]
 
 # Set toplevel
-set my_toplevel $::env(DESIGN)
+if { $wrapper == 1 } {
+    set my_toplevel $::env(DESIGN)wrapper
+} else {
+    set my_toplevel $::env(DESIGN)
+}
 
 # Set number of significant digits
 set report_default_significant_digits 6