More changes

src/ebu/ahbcacheinterface.sv

@@ -51,11 +51,11 @@ module ahbcacheinterface #(
   
   // cache interface
   input  logic [`PA_BITS-1:0] CacheBusAdr,            // Address of cache line
-  input logic [`LLEN-1:0]     CacheReadDataWordM,      // one word of cache line during a writeback
+  input  logic [`LLEN-1:0]    CacheReadDataWordM,     // One word of cache line during a writeback
   input  logic                CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$
   input  logic                Cacheable,              // Memory operation is cachable
   input  logic [1:0]          CacheBusRW,             // Cache bus operation, 01: writeback, 10: fetch
-  output logic                CacheBusAck,             // Handshack to $ indicating bus transaction completed
+  output logic                CacheBusAck,            // Handshake to $ indicating bus transaction completed
   output logic [LINELEN-1:0]  FetchBuffer,            // Register to hold beats of cache line as the arrive from bus
   output logic [AHBWLOGBWPL-1:0] BeatCount,           // Beat position within the cache line in the Address Phase
   output logic                SelBusBeat,             // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr

src/ebu/controllerinput.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// controller input stage
+// controllerinput.sv
 //
 // Written: Ross Thompson ross1728@gmail.com
 // Created:  August 31, 2022
@@ -40,7 +40,7 @@ module controllerinput #(
   input  logic                HRESETn,
   input  logic                Save,     // Two or more managers requesting (HTRANS != 00) at the same time.  Save the non-granted manager inputs
   input  logic                Restore,  // Restore a saved manager inputs when it is finally granted
-  input logic                 Disable,  // Supress HREADY to the non-granted manager
+  input  logic                Disable,  // Suppress HREADY to the non-granted manager
   output logic                Request,  // This manager is making a request
   // controller input
   input  logic [1:0]          HTRANSIn,  // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
@@ -48,14 +48,14 @@ module controllerinput #(
   input  logic [2:0]          HSIZEIn,   // Manager input. AHB transaction width
   input  logic [2:0]          HBURSTIn,  // Manager input. AHB burst length
   input  logic [`PA_BITS-1:0] HADDRIn,   // Manager input. AHB address
-  output logic                HREADYOut, // Indicate to manager the peripherial is not busy and another manager does not have priority
+  output logic                HREADYOut, // Indicate to manager the peripheral is not busy and another manager does not have priority
   // controller output
-  output logic [1:0]          HTRANSOut, // Aribrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
-  output logic                HWRITEOut, // Aribrated manager transaction. AHB 0: Read operation 1: Write operation 
-  output logic [2:0]          HSIZEOut,  // Aribrated manager transaction. AHB transaction width
-  output logic [2:0]          HBURSTOut, // Aribrated manager transaction. AHB burst length 
-  output logic [`PA_BITS-1:0] HADDROut,  // Aribrated manager transaction. AHB address
-  input logic                 HREADYIn   // Peripherial ready
+  output logic [1:0]          HTRANSOut, // Arbitrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
+  output logic                HWRITEOut, // Arbitrated manager transaction. AHB 0: Read operation 1: Write operation 
+  output logic [2:0]          HSIZEOut,  // Arbitrated manager transaction. AHB transaction width
+  output logic [2:0]          HBURSTOut, // Arbitrated manager transaction. AHB burst length 
+  output logic [`PA_BITS-1:0] HADDROut,  // Arbitrated manager transaction. AHB address
+  input  logic                HREADYIn   // Peripheral ready
 );
 
   logic                       HWRITESave;

src/ebu/ebufsmarb.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// ebufsmarb
+// ebufsmarb.sv
 //
 // Written: Ross Thompson ross1728@gmail.com
 // Created: 23 January 2023
@@ -86,7 +86,7 @@ module ebufsmarb (
   // Controller 1 (LSU)
   // When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state.
   // Once the LSU request is done the fsm returns to IDLE.  To prevent the LSU from regaining
-  // priority and re issuing the same memroy operation, the delayed IFUReqD squashes the LSU request.
+  // priority and re-issuing the same memory operation, the delayed IFUReqD squashes the LSU request.
   // This is necessary because the pipeline is stalled for the entire duration of both transactions,
   // and the LSU memory request will stil be active.
   flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD);

src/fpu/fdivsqrt/fdivsqrtexpcalc.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// fdivsqrtpreproc.sv
+// fdivsqrtexpcalc.sv
 //
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022