diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index e2e7d3696..38b1e6879 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -38,27 +38,27 @@ module ahbcacheinterface #( )( input logic HCLK, HRESETn, // bus interface controls - input logic HREADY, // AHB peripheral ready + input logic HREADY, // AHB peripheral ready output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ output logic HWRITE, // AHB 0: Read operation 1: Write operation output logic [2:0] HSIZE, // AHB transaction width output logic [2:0] HBURST, // AHB burst length // bus interface buses - input logic [`AHBW-1:0] HRDATA, // AHB read data + input logic [`AHBW-1:0] HRDATA, // AHB read data output logic [`PA_BITS-1:0] HADDR, // AHB address output logic [`AHBW-1:0] HWDATA, // AHB write data output logic [`AHBW/8-1:0] HWSTRB, // AHB byte mask // cache interface - input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line - input logic [`LLEN-1:0] CacheReadDataWordM, // one word of cache line during a writeback - input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ - input logic Cacheable, // Memory operation is cachable - input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch - output logic CacheBusAck, // Handshack to $ indicating bus transaction completed - output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus - output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase - output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr + input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line + input logic [`LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback + input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ + input logic Cacheable, // Memory operation is cachable + input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch + output logic CacheBusAck, // Handshake to $ indicating bus transaction completed + output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus + output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase + output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // uncached interface input logic [`PA_BITS-1:0] PAdr, // Physical address of uncached memory operation @@ -77,7 +77,7 @@ module ahbcacheinterface #( logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA - logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s + logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data genvar index; @@ -107,7 +107,7 @@ module ahbcacheinterface #( end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0]; mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]), - .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); + .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. @@ -119,5 +119,5 @@ module ahbcacheinterface #( buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed, - .HREADY, .HTRANS, .HWRITE, .HBURST); + .HREADY, .HTRANS, .HWRITE, .HBURST); endmodule diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index 579791032..1a9308dd4 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -32,21 +32,21 @@ module ahbinterface #( parameter LSU = 0 // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits )( - input logic HCLK, HRESETn, + input logic HCLK, HRESETn, // bus interface - input logic HREADY, // AHB peripheral ready + input logic HREADY, // AHB peripheral ready output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ output logic HWRITE, // AHB 0: Read operation 1: Write operation - input logic [`XLEN-1:0] HRDATA, // AHB read data + input logic [`XLEN-1:0] HRDATA, // AHB read data output logic [`XLEN-1:0] HWDATA, // AHB write data output logic [`XLEN/8-1:0] HWSTRB, // AHB byte mask // lsu/ifu interface - input logic Stall, // Core pipeline is stalled - input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting - input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write - input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word - input logic [`XLEN-1:0] WriteData, // IEU write data for a store + input logic Stall, // Core pipeline is stalled + input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting + input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write + input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word + input logic [`XLEN-1:0] WriteData, // IEU write data for a store output logic BusStall, // Bus is busy with an in flight memory operation output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer // Register to hold HRDATA after arriving from the bus diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index e0efcf3a3..7456cac8b 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -40,29 +40,29 @@ module buscachefsm #( input logic HRESETn, // IEU interface - input logic Stall, // Core pipeline is stalled - input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting - input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write - output logic BusStall, // Bus is busy with an in flight memory operation - output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt + input logic Stall, // Core pipeline is stalled + input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting + input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write + output logic BusStall, // Bus is busy with an in flight memory operation + output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt // ahb cache interface locals. - output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA + output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA // cache interface - input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch - output logic CacheBusAck, // Handshack to $ indicating bus transaction completed + input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch + output logic CacheBusAck, // Handshack to $ indicating bus transaction completed // lsu interface output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase output logic [AHBWLOGBWPL-1:0] BeatCountDelayed, // Beat within the cache line in the second (Data) cache stage - output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr + output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // BUS interface - input logic HREADY, // AHB peripheral ready - output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - output logic HWRITE, // AHB 0: Read operation 1: Write operation - output logic [2:0] HBURST // AHB burst length + input logic HREADY, // AHB peripheral ready + output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + output logic HWRITE, // AHB 0: Read operation 1: Write operation + output logic [2:0] HBURST // AHB burst length ); typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype; @@ -78,8 +78,8 @@ module buscachefsm #( logic CacheAccess; always_ff @(posedge HCLK) - if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; - else CurrState <= #1 NextState; + if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; + else CurrState <= #1 NextState; always_comb begin case(CurrState) diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv index a8c8e8308..6e3c27d3b 100644 --- a/src/ebu/controllerinput.sv +++ b/src/ebu/controllerinput.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// controller input stage +// controllerinput.sv // // Written: Ross Thompson ross1728@gmail.com // Created: August 31, 2022 @@ -36,26 +36,26 @@ module controllerinput #( parameter SAVE_ENABLED = 1 // 1: Save manager inputs if Save = 1, 0: Don't save inputs )( - input logic HCLK, - input logic HRESETn, - input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs - input logic Restore, // Restore a saved manager inputs when it is finally granted - input logic Disable, // Supress HREADY to the non-granted manager + input logic HCLK, + input logic HRESETn, + input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs + input logic Restore, // Restore a saved manager inputs when it is finally granted + input logic Disable, // Suppress HREADY to the non-granted manager output logic Request, // This manager is making a request // controller input - input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation - input logic [2:0] HSIZEIn, // Manager input. AHB transaction width - input logic [2:0] HBURSTIn, // Manager input. AHB burst length - input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address - output logic HREADYOut, // Indicate to manager the peripherial is not busy and another manager does not have priority + input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation + input logic [2:0] HSIZEIn, // Manager input. AHB transaction width + input logic [2:0] HBURSTIn, // Manager input. AHB burst length + input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address + output logic HREADYOut, // Indicate to manager the peripheral is not busy and another manager does not have priority // controller output - output logic [1:0] HTRANSOut, // Aribrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - output logic HWRITEOut, // Aribrated manager transaction. AHB 0: Read operation 1: Write operation - output logic [2:0] HSIZEOut, // Aribrated manager transaction. AHB transaction width - output logic [2:0] HBURSTOut, // Aribrated manager transaction. AHB burst length - output logic [`PA_BITS-1:0] HADDROut, // Aribrated manager transaction. AHB address - input logic HREADYIn // Peripherial ready + output logic [1:0] HTRANSOut, // Arbitrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + output logic HWRITEOut, // Arbitrated manager transaction. AHB 0: Read operation 1: Write operation + output logic [2:0] HSIZEOut, // Arbitrated manager transaction. AHB transaction width + output logic [2:0] HBURSTOut, // Arbitrated manager transaction. AHB burst length + output logic [`PA_BITS-1:0] HADDROut, // Arbitrated manager transaction. AHB address + input logic HREADYIn // Peripheral ready ); logic HWRITESave; diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index ec1a3d674..a61a3961f 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// ebufsmarb +// ebufsmarb.sv // // Written: Ross Thompson ross1728@gmail.com // Created: 23 January 2023 @@ -55,7 +55,7 @@ module ebufsmarb ( logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst logic BeatCntEn; - logic [3:0] BeatCount; // Position within a burst transfer + logic [3:0] BeatCount; // Position within a burst transfer logic BeatCntReset; logic [3:0] Threshold; // Number of beats derived from HBURST @@ -86,7 +86,7 @@ module ebufsmarb ( // Controller 1 (LSU) // When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state. // Once the LSU request is done the fsm returns to IDLE. To prevent the LSU from regaining - // priority and re issuing the same memroy operation, the delayed IFUReqD squashes the LSU request. + // priority and re-issuing the same memory operation, the delayed IFUReqD squashes the LSU request. // This is necessary because the pipeline is stalled for the entire duration of both transactions, // and the LSU memory request will stil be active. flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD); diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index 482fed842..aa8ae051d 100644 --- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// fdivsqrtpreproc.sv +// fdivsqrtexpcalc.sv // // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu // Modified:13 January 2022 @@ -30,11 +30,11 @@ module fdivsqrtexpcalc( input logic [`FMTBITS-1:0] Fmt, - input logic [`NE-1:0] Xe, Ye, - input logic Sqrt, - input logic XZero, - input logic [`DIVBLEN:0] ell, m, - output logic [`NE+1:0] Qe + input logic [`NE-1:0] Xe, Ye, + input logic Sqrt, + input logic XZero, + input logic [`DIVBLEN:0] ell, m, + output logic [`NE+1:0] Qe ); logic [`NE-2:0] Bias; logic [`NE+1:0] SXExp; @@ -42,28 +42,28 @@ module fdivsqrtexpcalc( logic [`NE+1:0] DExp; if (`FPSIZES == 1) begin - assign Bias = (`NE-1)'(`BIAS); + assign Bias = (`NE-1)'(`BIAS); end else if (`FPSIZES == 2) begin - assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); + assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); end else if (`FPSIZES == 3) begin - always_comb - case (Fmt) - `FMT: Bias = (`NE-1)'(`BIAS); - `FMT1: Bias = (`NE-1)'(`BIAS1); - `FMT2: Bias = (`NE-1)'(`BIAS2); - default: Bias = 'x; - endcase + always_comb + case (Fmt) + `FMT: Bias = (`NE-1)'(`BIAS); + `FMT1: Bias = (`NE-1)'(`BIAS1); + `FMT2: Bias = (`NE-1)'(`BIAS2); + default: Bias = 'x; + endcase end else if (`FPSIZES == 4) begin - always_comb - case (Fmt) - 2'h3: Bias = (`NE-1)'(`Q_BIAS); - 2'h1: Bias = (`NE-1)'(`D_BIAS); - 2'h0: Bias = (`NE-1)'(`S_BIAS); - 2'h2: Bias = (`NE-1)'(`H_BIAS); - endcase + always_comb + case (Fmt) + 2'h3: Bias = (`NE-1)'(`Q_BIAS); + 2'h1: Bias = (`NE-1)'(`D_BIAS); + 2'h0: Bias = (`NE-1)'(`S_BIAS); + 2'h2: Bias = (`NE-1)'(`H_BIAS); + endcase end assign SXExp = {2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - (`NE+2)'(`BIAS); assign SExp = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};