From d31c28e2a36ed27450ddcdb7125ce42f4a360012 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Fri, 12 Jan 2024 00:26:56 -0600 Subject: [PATCH 1/9] add csh setup.csh for increasing stack size --- setup.csh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/setup.csh b/setup.csh index 0508c36d0..82728f57c 100755 --- a/setup.csh +++ b/setup.csh @@ -46,4 +46,7 @@ extend PATH /usr/local/bin/verilator # Change this for your path to Verilator #set path = ($RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64 $path) #setenv LD_LIBRARY_PATH $RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas +# Verilator needs a larger stack to simulate CORE-V Wally +limit stacksize unlimited + echo "setup done" From dbe8394651f0c3959a9ed4006a8418cad9ab1323 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Fri, 12 Jan 2024 00:32:18 -0600 Subject: [PATCH 2/9] Update testbench-fp.sv to check result and flags for cvtint and cmp. This addresses fix for Issue #541. It also adds a temporary fix to avoid issues between tests. This will be fixed in an upcoming push where we use scanf instead of readmemh to help keep compatibility with Verilator. Additional testing is needed of new testbench-fp.sv before can push in new tb with scanf --- testbench/testbench-fp.sv | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 53001a4bc..e9aeb7ee6 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -957,23 +957,15 @@ module testbenchfp; $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); $stop; end - - // TestFloat sets the result to all 1's when there is an invalid result, however in - // http://www.jhauser.us/arithmetic/TestFloat-3/doc/TestFloat-general.html it says - // for an unsigned integer result 0 is also okay - // TestFloat outputs 800... for both the largest integer values for both positive and negitive numbers but - // the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff... - else if ( ((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) & ~FlagMatch ) begin - // ResMatch & FlagMatch checks the result again. It is checked within the - // test again to avoid issues related when the values change tests (e.g., f16_eq_rne -> f16_eq_rz) - if (~(ResMatch & FlagMatch)) begin - errors += 1; - $display("\nError in %s", Tests[TestNum]); - $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); - $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); - $stop; - end + // Check for conversion and comparisons + else if (((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) & + ~(ResMatch & FlagMatch) & (Ans[0] !== 1'bx)) begin + errors += 1; + $display("\nError in %s", Tests[TestNum]); + $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); + $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); + $stop; end if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof From e707eeb7c80c12dcbe86c41d293ad9caeceae989 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Fri, 12 Jan 2024 00:37:50 -0600 Subject: [PATCH 3/9] THis includes fix for special case when conversion from fp to int/long. The previous src did not test both the flags and result and so missed this subtle bug when an Invalid happens for this type of conversion. These results are indications of undefined behavior for these operations. All fp operations now passs when this update is fixed. Much of the information why these outputs should occur is somewhat alluded to by Pascal Cuoq originally from INSA in Lyon here: https://frama-c.com/2013/10/09/Overflow-float-integer.html --- src/fpu/postproc/specialcase.sv | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv index c8442595a..b765375d1 100644 --- a/src/fpu/postproc/specialcase.sv +++ b/src/fpu/postproc/specialcase.sv @@ -266,28 +266,34 @@ module specialcase import cvw::*; #(parameter cvw_t P) ( // integer result selection /////////////////////////////////////////////////////////////////////////////////////// + // Causes undefined behavior for invalid: + // unsigned: if invalid (e.g., negative fp to unsigned int, result should overflow and + // overflows to the maximum value + // signed: if invalid, result should overflow to maximum negative value + // but is undefined and used for information only + // select the overflow integer res // - negitive infinity and out of range negitive input - // | int | long | - // signed | -2^31 | -2^63 | - // unsigned | 0 | 0 | + // | int | long | + // signed | -2^31 | -2^63 | + // unsigned | 2^32-1 | 2^64-1 | // // - positive infinity and out of range positive input and NaNs // | int | long | - // signed | 2^31-1 | 2^63-1 | + // signed | -2^31 |-2^63 | // unsigned | 2^32-1 | 2^64-1 | // - // other: 32 bit unsinged res should be sign extended as if it were a signed number + // other: 32 bit unsigned res should be sign extended as if it were a signed number always_comb if(Signed) if(Xs&~NaNIn) // signed negitive if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}}; else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}}; else // signed positive - if(Int64) OfIntRes = {1'b0, {P.XLEN-1{1'b1}}}; - else OfIntRes = {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}}; + if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}}; + else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}}; else - if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b0}}; // unsigned negitive + if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b1}}; // unsigned negitive else OfIntRes = {P.XLEN{1'b1}}; // unsigned positive // select the integer output From 6226c3db96f62ab12204d3bbeb170a1ac73f1420 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Fri, 12 Jan 2024 07:50:13 -0800 Subject: [PATCH 4/9] Revert "Fixes for Issue #541" --- setup.csh | 3 --- src/fpu/postproc/specialcase.sv | 22 ++++++++-------------- testbench/testbench-fp.sv | 24 ++++++++++++++++-------- 3 files changed, 24 insertions(+), 25 deletions(-) diff --git a/setup.csh b/setup.csh index 82728f57c..0508c36d0 100755 --- a/setup.csh +++ b/setup.csh @@ -46,7 +46,4 @@ extend PATH /usr/local/bin/verilator # Change this for your path to Verilator #set path = ($RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64 $path) #setenv LD_LIBRARY_PATH $RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas -# Verilator needs a larger stack to simulate CORE-V Wally -limit stacksize unlimited - echo "setup done" diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv index b765375d1..c8442595a 100644 --- a/src/fpu/postproc/specialcase.sv +++ b/src/fpu/postproc/specialcase.sv @@ -266,34 +266,28 @@ module specialcase import cvw::*; #(parameter cvw_t P) ( // integer result selection /////////////////////////////////////////////////////////////////////////////////////// - // Causes undefined behavior for invalid: - // unsigned: if invalid (e.g., negative fp to unsigned int, result should overflow and - // overflows to the maximum value - // signed: if invalid, result should overflow to maximum negative value - // but is undefined and used for information only - // select the overflow integer res // - negitive infinity and out of range negitive input - // | int | long | - // signed | -2^31 | -2^63 | - // unsigned | 2^32-1 | 2^64-1 | + // | int | long | + // signed | -2^31 | -2^63 | + // unsigned | 0 | 0 | // // - positive infinity and out of range positive input and NaNs // | int | long | - // signed | -2^31 |-2^63 | + // signed | 2^31-1 | 2^63-1 | // unsigned | 2^32-1 | 2^64-1 | // - // other: 32 bit unsigned res should be sign extended as if it were a signed number + // other: 32 bit unsinged res should be sign extended as if it were a signed number always_comb if(Signed) if(Xs&~NaNIn) // signed negitive if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}}; else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}}; else // signed positive - if(Int64) OfIntRes = {1'b1, {P.XLEN-1{1'b0}}}; - else OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}}; + if(Int64) OfIntRes = {1'b0, {P.XLEN-1{1'b1}}}; + else OfIntRes = {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}}; else - if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b1}}; // unsigned negitive + if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b0}}; // unsigned negitive else OfIntRes = {P.XLEN{1'b1}}; // unsigned positive // select the integer output diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index e9aeb7ee6..53001a4bc 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -957,15 +957,23 @@ module testbenchfp; $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); $stop; end + + // TestFloat sets the result to all 1's when there is an invalid result, however in + // http://www.jhauser.us/arithmetic/TestFloat-3/doc/TestFloat-general.html it says + // for an unsigned integer result 0 is also okay - // Check for conversion and comparisons - else if (((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) & - ~(ResMatch & FlagMatch) & (Ans[0] !== 1'bx)) begin - errors += 1; - $display("\nError in %s", Tests[TestNum]); - $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); - $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); - $stop; + // TestFloat outputs 800... for both the largest integer values for both positive and negitive numbers but + // the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff... + else if ( ((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) & ~FlagMatch ) begin + // ResMatch & FlagMatch checks the result again. It is checked within the + // test again to avoid issues related when the values change tests (e.g., f16_eq_rne -> f16_eq_rz) + if (~(ResMatch & FlagMatch)) begin + errors += 1; + $display("\nError in %s", Tests[TestNum]); + $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); + $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); + $stop; + end end if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof From e6a25959364f8310c203d3b8604137d8c6489097 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 12 Jan 2024 11:05:06 -0600 Subject: [PATCH 5/9] Modified sv48 svadu test to work with 128MB rather than 2GB physical memory. --- .../rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S index 5cecb41ce..dcea1ff33 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S @@ -113,7 +113,7 @@ test_cases: .8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 11.3.1.3.2 .8byte 0x80200130, 0x0110DEADBEEF0077, write64_test # 11.3.1.3.2 .8byte 0x85212348, 0x0330DEADBEEF0440, write64_test # 11.3.1.3.3 -.8byte 0x88888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code +.8byte 0x87888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code .8byte 0x80203658, 0xDEADBEEFDEADBEEF, write64_test # 11.3.1.3.7(a) #.8byte 0x85bc0ab0, 0x0123456789abcdf0, write64_test # 11.3.1.1.4 @@ -188,7 +188,7 @@ test_cases: # test 11.3.1.3.5 eXecute flag # executes on pages with X = 1 already tested in 11.3.1.3.1 -.8byte 0x010088888000, 0x2, executable_test # execute fault when X=0 +.8byte 0x010087888000, 0x2, executable_test # execute fault when X=0 # In the following two tests, SVADU is supported, so the hardware handles the A/D bits From 0b2af0c99a49cc760e94981a950857fd57af0f66 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 12 Jan 2024 20:00:21 -0600 Subject: [PATCH 6/9] Modifed the sv39 tests so they work with just 128MiB physical memory. --- .../rv64i_m/privilege/src/WALLY-mmu-sv39-01.S | 6 +++--- .../privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S | 6 +++--- .../rv64i_m/privilege/src/WALLY-mmu-sv48-01.S | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S index 548911c0c..d9ef62141 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S @@ -87,8 +87,8 @@ test_cases: .8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage # second page table to check context switches with satp -.8byte 0x8FFFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage -.8byte 0x8FFFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around) +.8byte 0x87FFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage +.8byte 0x87FFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around) # test 11.3.1.1.2 write values to Paddrs in each page # each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments. @@ -192,7 +192,7 @@ test_cases: # test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID) // *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB -.8byte 0x8FFFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table +.8byte 0x87FFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table .8byte 0x200AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping # test 11.3.1.4.2 Test Global mapping diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S index 56d36aa6a..2fbdf48ca 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S @@ -108,8 +108,8 @@ test_cases: .8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage # second page table to check context switches with satp -.8byte 0x8FFFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage -.8byte 0x8FFFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around) +.8byte 0x87FFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage +.8byte 0x87FFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around) # test 11.3.1.1.2 write values to Paddrs in each page # each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments. @@ -249,7 +249,7 @@ test_cases: # test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID) // *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB -.8byte 0x8FFFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table +.8byte 0x87FFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table .8byte 0x200AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping # test 11.3.1.4.2 Test Global mapping diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S index bb49f3e7a..b6161fb8b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S @@ -113,7 +113,7 @@ test_cases: .8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 11.3.1.3.2 .8byte 0x80200130, 0x0110DEADBEEF0077, write64_test # 11.3.1.3.2 .8byte 0x85212348, 0x0330DEADBEEF0440, write64_test # 11.3.1.3.3 -.8byte 0x88888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code +.8byte 0x87888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code .8byte 0x80203AA0, 0x0440DEADBEEF0BB0, write64_test # 11.3.1.3.7 # test 11.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test) @@ -187,7 +187,7 @@ test_cases: # test 11.3.1.3.5 eXecute flag # executes on pages with X = 1 already tested in 11.3.1.3.1 -.8byte 0x010088888000, 0x2, executable_test # execute fault when X=0 +.8byte 0x010087888000, 0x2, executable_test # execute fault when X=0 # In the following two tests, SVADU is not supported, so the software handles the A/D bits # Since SVADU is 0, Accesses to A/D=0 causes a fault for the trap handler to fix those bits From ba95e5fafdbff857173c31400bfb57655792ba42 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 12 Jan 2024 20:01:05 -0600 Subject: [PATCH 7/9] Reduced the rv64gc config to 128MiB memory. --- config/rv64gc/config.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index a8b7f1b05..af6e4aebd 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -107,7 +107,7 @@ localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; localparam BOOTROM_PRELOAD = 1'b0; localparam UNCORE_RAM_SUPPORTED = 1'b1; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; -localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; localparam UNCORE_RAM_PRELOAD = 1'b0; localparam EXT_MEM_SUPPORTED = 1'b0; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; From d7b016e8f349c0117cdf26473bcd029d5f176f88 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 12 Jan 2024 18:12:52 -0800 Subject: [PATCH 8/9] Cleaned up Zicond implementation --- src/ieu/alu.sv | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index b13c3a65c..4c296fda2 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -101,11 +101,16 @@ module alu import cvw::*; #(parameter cvw_t P) ( // Zicond block if (P.ZICOND_SUPPORTED) begin: zicond - logic BZero, KillB; + logic BZero; + assign BZero = (B == 0); // check if rs2 = 0 // Create a signal that is 0 when czero.* instruction should clear result // If B = 0 for czero.eqz or if B != 0 for czero.nez - assign KillB = BZero & CZero[0] | ~BZero & CZero[1]; - assign ZeroCondMaskInvB = |CZero ? {P.XLEN{~KillB}} : CondMaskInvB; // extend to full width + always_comb + case (CZero) + 2'b01: ZeroCondMaskInvB = {P.XLEN{~BZero}}; // czero.eqz: kill if B = 0 + 2'b10: ZeroCondMaskInvB = {P.XLEN{BZero}}; // czero.nez: kill if B != 0 + default: ZeroCondMaskInvB = CondMaskInvB; // otherwise normal behavior + endcase end else assign ZeroCondMaskInvB = CondMaskInvB; // no masking if Zicond is not supported endmodule From a9acb5f269635d0bec9a5d19dc7e31a9a818b14b Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 12 Jan 2024 18:13:11 -0800 Subject: [PATCH 9/9] Added comments with a way to build Sail on RedHat --- bin/wally-tool-chain-install.sh | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index f690bfac1..7ccb1a138 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -137,6 +137,27 @@ sudo make install # package manager. Sail has so many dependencies that it can be difficult to install. # This script works for Ubuntu. +# Alex Solomatnikov found these commands worked to build Sail for Centos 8 on 1/12/24 +#sudo su - +#dnf install ocaml.x86_64 +#pip3 install z3-solver +#wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh +#sh install.sh +#opam init +#exit +#ocaml -version +#opam switch create 5.1.0 +#eval $(opam config env) +#git clone --recurse-submodules git@github.com:riscv/sail-riscv.git +#cd sail-riscv +#make +#ARCH=RV32 make +#ARCH=RV64 make +#git log -1 +#cp -p c_emulator/riscv_sim_RV* /tools/sail-riscv/d7a3d8012fd579f40e53a29569141d72dd5e0c32/bin/. + + +# This was an earlier attemp to prepare to install Sail on RedHat 8 # Do these commands only for RedHat / Rocky 8 to build from source. #cd $RISCV #git clone https://github.com/Z3Prover/z3.git