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Added spi debugger to build script.
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@ -98,6 +98,7 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v
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if {$board=="ArtyA7"} {
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if {$board=="ArtyA7"} {
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#source ../constraints/small-debug.xdc
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#source ../constraints/small-debug.xdc
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#source ../constraints/small-debug-rvvi.xdc
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#source ../constraints/small-debug-rvvi.xdc
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#source ../constraints/small-debug-spi.xdc
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} else {
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} else {
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#source ../constraints/vcu-small-debug.xdc
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#source ../constraints/vcu-small-debug.xdc
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#source ../constraints/small-debug.xdc
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#source ../constraints/small-debug.xdc
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