diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index 5207680df..5151b0e77 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -98,6 +98,7 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v
 if {$board=="ArtyA7"} {
     #source ../constraints/small-debug.xdc
     #source ../constraints/small-debug-rvvi.xdc
+    #source ../constraints/small-debug-spi.xdc
 } else {
     #source ../constraints/vcu-small-debug.xdc
     #source ../constraints/small-debug.xdc