Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register.

Browse Source
This commit is contained in:
Ross Thompson 2021-12-21 15:59:56 -06:00
parent 4ae15bf5e4
commit 50e4463a7f
2 changed files with 10 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
wally-pipelined/src/cache/dcachefsm.sv vendored
View File

@ -169,7 +169,7 @@ module dcachefsm
end end
// Flush dcache to next level of memory // Flush dcache to next level of memory
else if(FlushDCacheM & ~(ExceptionM | PendingInterruptM)) begin else if(FlushDCacheM) begin
NextState = STATE_FLUSH; NextState = STATE_FLUSH;
DCacheStall = 1'b1; DCacheStall = 1'b1;
SelAdrM = 2'b11; SelAdrM = 2'b11;
@ -178,7 +178,7 @@ module dcachefsm
end end
// amo hit // amo hit
else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin else if(AtomicM[1] & (&MemRWM) & CacheableM & CacheHit) begin
SelAdrM = 2'b10; SelAdrM = 2'b10;
DCacheStall = 1'b0; DCacheStall = 1'b0;
@ -194,7 +194,7 @@ module dcachefsm
end end
end end
// read hit valid cached // read hit valid cached
else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin else if(MemRWM[1] & CacheableM & CacheHit) begin
DCacheStall = 1'b0; DCacheStall = 1'b0;
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
@ -207,7 +207,7 @@ module dcachefsm
end end
end end
// write hit valid cached // write hit valid cached
else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin else if (MemRWM[0] & CacheableM & CacheHit) begin
SelAdrM = 2'b10; SelAdrM = 2'b10;
DCacheStall = 1'b0; DCacheStall = 1'b0;
SRAMWordWriteEnableM = 1'b1; SRAMWordWriteEnableM = 1'b1;
@ -223,29 +223,25 @@ module dcachefsm
end end
end end
// read or write miss valid cached // read or write miss valid cached
else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit) begin else if((|MemRWM) & CacheableM & ~CacheHit) begin
NextState = STATE_MISS_FETCH_WDV; NextState = STATE_MISS_FETCH_WDV;
CntReset = 1'b1; CntReset = 1'b1;
DCacheStall = 1'b1; DCacheStall = 1'b1;
end end
// uncached write // uncached write
else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM)) begin else if(MemRWM[0] & ~CacheableM) begin
NextState = STATE_UNCACHED_WRITE; NextState = STATE_UNCACHED_WRITE;
CntReset = 1'b1; CntReset = 1'b1;
DCacheStall = 1'b1; DCacheStall = 1'b1;
AHBWrite = 1'b1; AHBWrite = 1'b1;
end end
// uncached read // uncached read
else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM)) begin else if(MemRWM[1] & ~CacheableM) begin
NextState = STATE_UNCACHED_READ; NextState = STATE_UNCACHED_READ;
CntReset = 1'b1; CntReset = 1'b1;
DCacheStall = 1'b1; DCacheStall = 1'b1;
AHBRead = 1'b1; AHBRead = 1'b1;
end end
// fault
else if(AnyCPUReqM & (ExceptionM | PendingInterruptM)) begin
NextState = STATE_READY;
end
else NextState = STATE_READY; else NextState = STATE_READY;
end end

4
wally-pipelined/src/lsu/lsu.sv
View File

@ -198,7 +198,9 @@ module lsu
assign SelReplayCPURequest = (NextState == STATE_T0_REPLAY) | (NextState == STATE_T0_FAULT_REPLAY); assign SelReplayCPURequest = (NextState == STATE_T0_REPLAY) | (NextState == STATE_T0_FAULT_REPLAY);
assign SelHPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) | assign SelHPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
(CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS); (CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
assign IgnoreRequest = CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM); assign IgnoreRequest = (CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | ExceptionM | PendingInterruptM)) |
((CurrState == STATE_T0_REPLAY | CurrState == STATE_T0_FAULT_REPLAY)
& (ExceptionM | PendingInterruptM));
assign WalkerInstrPageFaultF = WalkerInstrPageFaultRaw | CurrState == STATE_T0_FAULT_REPLAY; assign WalkerInstrPageFaultF = WalkerInstrPageFaultRaw | CurrState == STATE_T0_FAULT_REPLAY;