mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
David Harris
commit
50b44b4416
@ -88,14 +88,14 @@ for test in tests32ic:
|
|||||||
grepstr="All tests ran without failures")
|
grepstr="All tests ran without failures")
|
||||||
configs.append(tc)
|
configs.append(tc)
|
||||||
|
|
||||||
tests32e = ["wally32e"]
|
#tests32e = ["wally32e"]
|
||||||
for test in tests32e:
|
#for test in tests32e:
|
||||||
tc = TestCase(
|
# tc = TestCase(
|
||||||
name=test,
|
# name=test,
|
||||||
variant="rv32e",
|
# variant="rv32e",
|
||||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32e "+test+"\n!",
|
# cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32e "+test+"\n!",
|
||||||
grepstr="All tests ran without failures")
|
# grepstr="All tests ran without failures")
|
||||||
configs.append(tc)
|
# configs.append(tc)
|
||||||
|
|
||||||
|
|
||||||
import os
|
import os
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
@ -28,7 +28,8 @@ do
|
|||||||
echo -e "Check $(printf %-24s ${stub}) \e[33m ... IGNORE \e[39m"
|
echo -e "Check $(printf %-24s ${stub}) \e[33m ... IGNORE \e[39m"
|
||||||
continue
|
continue
|
||||||
fi
|
fi
|
||||||
diff --ignore-case --strip-trailing-cr ${ref} ${sig} &> /dev/null
|
# KMG: changed diff snippet to a grep that will strip comments with '//' and '#' out of the reference file
|
||||||
|
diff --ignore-case --ignore-trailing-space --strip-trailing-cr <(grep -o '^[^//#]*' ${ref}) ${sig} &> /dev/null
|
||||||
if [ $? == 0 ]
|
if [ $? == 0 ]
|
||||||
then
|
then
|
||||||
echo -e "\e[32m ... OK \e[39m"
|
echo -e "\e[32m ... OK \e[39m"
|
||||||
|
|||||||
@ -63,8 +63,9 @@ copy:
|
|||||||
$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
|
$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
|
||||||
$(info <<<<<<<<<<<<<<<<<<<<<<<<<<<< COPYING REFERENCES WITHOUT SIMULATING >>>>>>>>>>>>>>>>>>>>>>>>>>>>)
|
$(info <<<<<<<<<<<<<<<<<<<<<<<<<<<< COPYING REFERENCES WITHOUT SIMULATING >>>>>>>>>>>>>>>>>>>>>>>>>>>>)
|
||||||
$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
|
$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
|
||||||
$(V) echo "Copying References without simulating"
|
$(V) echo "Copying References without simulating for the following tests:"
|
||||||
$(V) for test in $(target_tests_nosim); do cp $(ref_dir)/$$test.reference_output $(work_dir_isa)/$$test.signature.output; done
|
$(V) echo $(target_tests_nosim)
|
||||||
|
$(V) for test in $(target_tests_nosim); do grep -o '^[^//#]*' $(ref_dir)/$$test.reference_output > $(work_dir_isa)/$$test.signature.output; done
|
||||||
|
|
||||||
compile: $(combined_elf)
|
compile: $(combined_elf)
|
||||||
run: $(target_log)
|
run: $(target_log)
|
||||||
|
|||||||
@ -28,48 +28,11 @@
|
|||||||
# Description: Makefrag for RV32I architectural tests
|
# Description: Makefrag for RV32I architectural tests
|
||||||
|
|
||||||
rv32i_sc_tests = \
|
rv32i_sc_tests = \
|
||||||
E-add-01 \
|
|
||||||
E-addi-01 \
|
|
||||||
E-and-01 \
|
|
||||||
E-andi-01 \
|
|
||||||
E-auipc-01 \
|
|
||||||
E-beq-01 \
|
|
||||||
E-bge-01 \
|
|
||||||
E-bgeu-01 \
|
|
||||||
E-blt-01 \
|
|
||||||
E-bltu-01 \
|
|
||||||
E-bne-01 \
|
|
||||||
E-jal-01 \
|
|
||||||
E-jalr-01 \
|
|
||||||
E-lb-align-01 \
|
|
||||||
E-lbu-align-01 \
|
|
||||||
E-lh-align-01 \
|
|
||||||
E-lhu-align-01 \
|
|
||||||
E-lui-01 \
|
|
||||||
E-lw-align-01 \
|
|
||||||
E-or-01 \
|
|
||||||
E-ori-01 \
|
|
||||||
E-sb-align-01 \
|
|
||||||
E-sh-align-01 \
|
|
||||||
E-sll-01 \
|
|
||||||
E-slli-01 \
|
|
||||||
E-slt-01 \
|
|
||||||
E-slti-01 \
|
|
||||||
E-sltiu-01 \
|
|
||||||
E-sltu-01 \
|
|
||||||
E-sra-01 \
|
|
||||||
E-srai-01 \
|
|
||||||
E-srl-01 \
|
|
||||||
E-srli-01 \
|
|
||||||
E-sub-01 \
|
|
||||||
E-sw-align-01 \
|
|
||||||
E-xor-01 \
|
|
||||||
E-xori-01 \
|
|
||||||
WALLY-ADD \
|
WALLY-ADD \
|
||||||
WALLY-SUB \
|
WALLY-SLT \
|
||||||
WALLY-SLT \
|
|
||||||
WALLY-SLTU \
|
WALLY-SLTU \
|
||||||
WALLY-XOR
|
WALLY-SUB \
|
||||||
|
WALLY-XOR
|
||||||
|
|
||||||
rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
|
rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
|
||||||
|
|
||||||
|
|||||||
@ -31,7 +31,9 @@ rv64i_sc_tests = \
|
|||||||
WALLY-MMU-SV39 \
|
WALLY-MMU-SV39 \
|
||||||
WALLY-MMU-SV48 \
|
WALLY-MMU-SV48 \
|
||||||
WALLY-PMP \
|
WALLY-PMP \
|
||||||
WALLY-minfo-01
|
WALLY-minfo-01 \
|
||||||
|
WALLY-CSR-permission-s-01 \
|
||||||
|
WALLY-CSR-permission-u-01
|
||||||
|
|
||||||
target_tests_nosim = WALLY-PMA \
|
target_tests_nosim = WALLY-PMA \
|
||||||
|
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,104 +1,104 @@
|
|||||||
0000000b
|
0000000b # Test 12.3.1.1.3: ecall from going to S mode from M mode
|
||||||
00000000
|
00000000
|
||||||
beef0000
|
beef0000 # 7 read test successes
|
||||||
0000dead
|
0000dead
|
||||||
beef0055
|
beef0055 # read 2
|
||||||
0880dead
|
0880dead
|
||||||
beef0033
|
beef0033 # read 3
|
||||||
0990dead
|
0990dead
|
||||||
beef0077
|
beef0077 # read 4
|
||||||
0110dead
|
0110dead
|
||||||
beef0099
|
beef0099 # read 5
|
||||||
0220dead
|
0220dead
|
||||||
beef0440
|
beef0440 # read 6
|
||||||
0330dead
|
0330dead
|
||||||
beef0bb0
|
beef0bb0 # read 7
|
||||||
0440dead
|
0440dead
|
||||||
beef0000
|
beef0000 # Test 12.3.1.1.4: 3 read test successes
|
||||||
0000dead
|
0000dead
|
||||||
beef0055
|
beef0055 # read 2
|
||||||
0880dead
|
0880dead
|
||||||
beef0099
|
beef0099 # read 3
|
||||||
0220dead
|
0220dead
|
||||||
0000000d
|
0000000d # Test 12.3.1.2.1: 2 read tests with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # read 2
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # Test 12.3.1.2.2: read test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000f
|
0000000f # Test 12.3.1.2.3: write test with page fault
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # Test 12.3.1.2.4: read test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # Test 12.3.1.2.5: 2 read tests with page faults
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # read 2
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000111
|
00000111 # Test 12.3.1.3.1: execute test success
|
||||||
00000000
|
00000000
|
||||||
00000009
|
00000009 # ecall from going to U mode from S mode
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # read test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000c
|
0000000c # execute test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
beef0033
|
beef0033 # Test 12.3.1.3.2: read test success
|
||||||
0990dead
|
0990dead
|
||||||
00000008
|
00000008 # ecall from going to S mode from U mode
|
||||||
00000000
|
00000000
|
||||||
beef0077
|
beef0077 # read test success
|
||||||
0110dead
|
0110dead
|
||||||
0000000c
|
0000000c # execute test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # read test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # Test 12.3.1.3.3: read test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
beef0440
|
beef0440 # read test success
|
||||||
0330dead
|
0330dead
|
||||||
beef0110
|
beef0110 # Test 12.3.1.3.4: read test success
|
||||||
0440dead
|
0440dead
|
||||||
0000000f
|
0000000f # write test with page fault
|
||||||
00000000
|
00000000
|
||||||
0000000c
|
0000000c # Test 12.3.1.3.5: execute test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000f
|
0000000f # Test 12.3.1.3.6: write test with page fault
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # read test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000f
|
0000000f # Test 12.3.1.3.7: write test with page fault
|
||||||
00000000
|
00000000
|
||||||
beef0bb0
|
beef0bb0 # read test success
|
||||||
0440dead
|
0440dead
|
||||||
00000009
|
00000009 # ecall from test termination from S mode
|
||||||
00000000
|
00000000
|
||||||
deadbeef
|
deadbeef # rest of the output space
|
||||||
deadbeef
|
deadbeef
|
||||||
deadbeef
|
deadbeef
|
||||||
deadbeef
|
deadbeef
|
||||||
|
|||||||
@ -1,112 +1,112 @@
|
|||||||
0000000b
|
0000000b # Test 12.3.1.1.3: ecall from going to S mode from M mode
|
||||||
00000000
|
00000000
|
||||||
beef0cc0
|
beef0cc0 # 8 read test successes
|
||||||
0ee0dead
|
0ee0dead
|
||||||
beef0000
|
beef0000 # read 2
|
||||||
0000dead
|
0000dead
|
||||||
beef0055
|
beef0055 # read 3
|
||||||
0880dead
|
0880dead
|
||||||
beef0033
|
beef0033 # read 4
|
||||||
0990dead
|
0990dead
|
||||||
beef0077
|
beef0077 # read 5
|
||||||
0110dead
|
0110dead
|
||||||
beef0099
|
beef0099 # read 6
|
||||||
0220dead
|
0220dead
|
||||||
beef0440
|
beef0440 # read 7
|
||||||
0330dead
|
0330dead
|
||||||
beef0bb0
|
beef0bb0 # read 8
|
||||||
0440dead
|
0440dead
|
||||||
beef0cc0
|
beef0cc0 # Test 12.3.1.1.4: 4 read test successes
|
||||||
0ee0dead
|
0ee0dead
|
||||||
beef0000
|
beef0000 # read 2
|
||||||
0000dead
|
0000dead
|
||||||
beef0055
|
beef0055 # read 3
|
||||||
0880dead
|
0880dead
|
||||||
beef0099
|
beef0099 # read 4
|
||||||
0220dead
|
0220dead
|
||||||
0000000d
|
0000000d # Test 12.3.1.2.1: 2 read tests with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # read 2
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # Test 12.3.1.2.2: read test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000f
|
0000000f # Test 12.3.1.2.3: write test with page fault
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # Test 12.3.1.2.4: read test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # Test 12.3.1.2.5: 3 read tests with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # read 2
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # read 3
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000111
|
00000111 # Test 12.3.1.3.1: Execute test success
|
||||||
00000000
|
00000000
|
||||||
00000009
|
00000009 # ecall from going to U mode from S mode
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # read test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000c
|
0000000c # execute test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
beef0033
|
beef0033 # Test 12.3.1.3.2: read test success
|
||||||
0990dead
|
0990dead
|
||||||
00000008
|
00000008 # ecall from going to S mode from U mode
|
||||||
00000000
|
00000000
|
||||||
beef0077
|
beef0077 # read test success
|
||||||
0110dead
|
0110dead
|
||||||
0000000c
|
0000000c # execute test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # read test with page fault`
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # Test 12.3.1.3.3: read test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
beef0440
|
beef0440 # read test success
|
||||||
0330dead
|
0330dead
|
||||||
beef0110
|
beef0110 # Test 12.3.1.3.4: read test success
|
||||||
0440dead
|
0440dead
|
||||||
0000000f
|
0000000f # write test with page fault
|
||||||
00000000
|
00000000
|
||||||
0000000c
|
0000000c # Test 12.3.1.3.5: executable test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000f
|
0000000f # Test 12.3.1.3.6: write test with page fault
|
||||||
00000000
|
00000000
|
||||||
0000000d
|
0000000d # read test with page fault
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000f
|
0000000f # Test 12.3.1.3.7: write test with page fault
|
||||||
00000000
|
00000000
|
||||||
beef0bb0
|
beef0bb0 # read test success
|
||||||
0440dead
|
0440dead
|
||||||
00000009
|
00000009 # ecall from test termination in S mode.
|
||||||
00000000
|
00000000
|
||||||
deadbeef
|
deadbeef # rest of the output space
|
||||||
deadbeef
|
deadbeef
|
||||||
deadbeef
|
deadbeef
|
||||||
deadbeef
|
deadbeef
|
||||||
|
|||||||
@ -1,148 +1,148 @@
|
|||||||
beef00b4
|
beef00b4 # Test 12.3.2.1: read 64 bits success in CLINT
|
||||||
0000dead
|
0000dead # all of these read successes are also confirming successful writes
|
||||||
beef00b5
|
beef00b5 # read 32 bits success in CLINT (sign extended)
|
||||||
ffffffff
|
ffffffff
|
||||||
000000b6
|
000000b6 # read 16 bits success in CLINT
|
||||||
00000000
|
00000000
|
||||||
ffffffb7
|
ffffffb7 # read 8 bits success in CLINT (sign extended)
|
||||||
ffffffff
|
ffffffff
|
||||||
00000001
|
00000001 # execute test with access fault in CLINT
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write 64 bits with access fault in PLIC
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read 64 bits with access fault in PLIC
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000002
|
00000002 # read 32 bits success in PLIC (confriming 32 bit write)
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write 16 bits with access fault in PLIC
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read 16 bits with access fault in PLIC
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write 8 bits with access fault in PLIC
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read 8 bits with access fault in PLIC
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000001
|
00000001 # execute test with access fault in PLIC
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write 64 bits with access fault in UART
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read 64 bits with access fault in UART
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write 32 bits with access fault in UART
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read 32 bits with access fault in UART
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write 16 bits with access fault in UART
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read 16 bits with access fault in UART
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
ffffffbf
|
ffffffbf # read 8 bits success in UART (confirming 8 bit write)
|
||||||
ffffffff
|
ffffffff
|
||||||
00000001
|
00000001 # execute test with access fault in UART
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write 64 bits with access fault in GPIO
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read 64 bits with access fault in GPIO
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
beef00c1
|
beef00c1 # read 32 bits success in GPIO (confirming 32 bit write)
|
||||||
ffffffff
|
ffffffff
|
||||||
00000007
|
00000007 # write 16 bits with access fault in GPIO
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read 16 bits with access fault in GPIO
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write 8 bits with access fault in GPIO
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read 8 bits with access fault in GPIO
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000001
|
00000001 # execute test with access fault in GPIO
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write test with access fault in random memory location
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read test with access fault in random memory location
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000001
|
00000001 # execute test with access fault in random memory location
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write test with access fault just after BOOTROM
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read test with access fault just after BOOTROM
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000001
|
00000001 # execute test with access fault just after BOOTROM
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write test with access fault just after CLINT
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read test with access fault just after CLINT
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000001
|
00000001 # execute test with access fault just after CLINT
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write test with access fault just after PLIC
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read test with access fault just after PLIC
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000001
|
00000001 # execute test with access fault just after PLIC
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write test with access fault just after UART
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read test with access fault just after UART
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000001
|
00000001 # execute test with access fault just after UART
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write test with access fault just after GPIO
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read test with access fault just after GPIO
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000001
|
00000001 # execute test with access fault just after GPIO
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
0000000b
|
0000000b # ecall from terminating tests in M mode
|
||||||
00000000
|
00000000
|
||||||
deadbeef
|
deadbeef
|
||||||
deadbeef
|
deadbeef
|
||||||
|
|||||||
@ -1,58 +1,58 @@
|
|||||||
0fffffff
|
0fffffff # Test 12.3.2.2.1: writeback of value written to PMPADDR0
|
||||||
|
00000000
|
||||||
|
20040000 # writeback of value written to PMPADDR1
|
||||||
00000000
|
00000000
|
||||||
20040000
|
2004003f # writeback of value written to PMPADDR2
|
||||||
00000000
|
00000000
|
||||||
2004003f
|
20040080 # writeback of value written to PMPADDR3
|
||||||
00000000
|
00000000
|
||||||
20040080
|
20040084 # writeback of value written to PMPADDR4
|
||||||
00000000
|
00000000
|
||||||
20040084
|
200400c0 # writeback of value written to PMPADDR5
|
||||||
00000000
|
00000000
|
||||||
200400c0
|
2004013f # writeback of value written to PMPADDR6
|
||||||
00000000
|
00000000
|
||||||
2004013f
|
2fffffff # writeback of value written to PMPADDR15
|
||||||
00000000
|
00000000
|
||||||
2fffffff
|
0009001f # writeback of value written to PMPCFG0
|
||||||
00000000
|
|
||||||
0009001f
|
|
||||||
0018900c
|
0018900c
|
||||||
00000000
|
00000000 # writeback of value written to PMPCFG2
|
||||||
1f000000
|
1f000000
|
||||||
0009001f
|
0009001f # old value of PMPCFG0 after failed write to locked out region
|
||||||
0018900c
|
0018900c
|
||||||
200400c0
|
200400c0 # old value of PMPADDR5 after failed write to locked out region
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # Test 12.3.2.2.2: read test with access fault to region with L=1, R=0
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00600dbb
|
00600dbb # read test success from region with L=X=W=R=0
|
||||||
00000000
|
00000000
|
||||||
0000000b
|
0000000b # Test 12.3.2.2.3: ecall from going to S mode from M mode
|
||||||
00000000
|
00000000
|
||||||
00600d15
|
00600d15 # read test success from RW range (confirming previous write)
|
||||||
00000000
|
00000000
|
||||||
00600d02
|
00600d02 # read test success from outside the edge of a read only range
|
||||||
00000000
|
00000000
|
||||||
00600d12
|
00600d12 # read test success from outside the other edge of a read only range
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write test with access fault in read only range
|
||||||
00000000
|
00000000
|
||||||
00600daa
|
00600daa # read success from read only range
|
||||||
00000000
|
00000000
|
||||||
00000007
|
00000007 # write test with access fault in no-access range
|
||||||
00000000
|
00000000
|
||||||
00000005
|
00000005 # read test with access fault in no-access range
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000001
|
00000001 # execute test with access fault in no-execute range
|
||||||
00000000
|
00000000
|
||||||
00000bad
|
00000bad
|
||||||
00000000
|
00000000
|
||||||
00000111
|
00000111 # execute sucess when X=1
|
||||||
00000000
|
00000000
|
||||||
00000009
|
00000009 # ecall from terminating tests in S mode
|
||||||
00000000
|
00000000
|
||||||
deadbeef
|
deadbeef
|
||||||
deadbeef
|
deadbeef
|
||||||
|
|||||||
@ -1,20 +1,20 @@
|
|||||||
00000002
|
00000002 # Test 5.2.3.1: write to read-only CSR failed with illegal instruction
|
||||||
00000000
|
00000000
|
||||||
00000011
|
00000011 # confirm read-only permissions of mvendorid
|
||||||
00000000
|
00000000
|
||||||
00000002
|
00000002 # write to read-only CSR failed with illegal instruction
|
||||||
00000000
|
00000000
|
||||||
00000011
|
00000011 # confirm read-only permissions of marchid
|
||||||
00000000
|
00000000
|
||||||
00000002
|
00000002 # write to read-only CSR failed with illegal instruction
|
||||||
00000000
|
00000000
|
||||||
00000011
|
00000011 # confirm read-only permissions of mimpid
|
||||||
00000000
|
00000000
|
||||||
00000002
|
00000002 # write to read-only CSR failed with illegal instruction
|
||||||
00000000
|
00000000
|
||||||
00000011
|
00000011 # confirm read-only permissions of mhartid
|
||||||
00000000
|
00000000
|
||||||
0000000b
|
0000000b # ecall from terminating tests in M mode
|
||||||
00000000
|
00000000
|
||||||
deadbeef
|
deadbeef
|
||||||
deadbeef
|
deadbeef
|
||||||
|
|||||||
@ -0,0 +1,153 @@
|
|||||||
|
///////////////////////////////////////////
|
||||||
|
//
|
||||||
|
// WALLY-CSR-permissions
|
||||||
|
//
|
||||||
|
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||||
|
//
|
||||||
|
// Created 2022-02-05
|
||||||
|
//
|
||||||
|
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||||
|
//
|
||||||
|
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||||
|
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||||
|
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||||
|
// is furnished to do so, subject to the following conditions:
|
||||||
|
//
|
||||||
|
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||||
|
//
|
||||||
|
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||||
|
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||||
|
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||||
|
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
///////////////////////////////////////////
|
||||||
|
|
||||||
|
#include "WALLY-TEST-MACROS-64.h"
|
||||||
|
|
||||||
|
INIT_TESTS
|
||||||
|
|
||||||
|
# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode.
|
||||||
|
|
||||||
|
# *** several of these appear not to be implemented in the assembler?
|
||||||
|
# I get "assembler messages: error: unkown CSR" with many of them.
|
||||||
|
|
||||||
|
goto_s_mode 0x0, 0x0
|
||||||
|
|
||||||
|
# Attempt to write 0xbad to each of these CSRs and read the value back
|
||||||
|
# should result in an illegal instruction for the write and read, respectively
|
||||||
|
|
||||||
|
# Machine information Registers
|
||||||
|
write_read_csr mvendorid, 0xbad
|
||||||
|
write_read_csr marchid, 0xbad
|
||||||
|
write_read_csr mimpid, 0xbad
|
||||||
|
write_read_csr mhartid, 0xbad
|
||||||
|
# write_read_csr mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
|
||||||
|
|
||||||
|
# Machine Trap Setup
|
||||||
|
write_read_csr mstatus, 0xbad
|
||||||
|
write_read_csr misa, 0xbad
|
||||||
|
write_read_csr medeleg, 0xbad
|
||||||
|
write_read_csr mideleg, 0xbad
|
||||||
|
write_read_csr mie, 0xbad
|
||||||
|
write_read_csr mtvec, 0xbad
|
||||||
|
write_read_csr mcounteren, 0xbad
|
||||||
|
|
||||||
|
# Machine Trap Handling
|
||||||
|
write_read_csr mscratch, 0xbad
|
||||||
|
write_read_csr mepc, 0xbad
|
||||||
|
write_read_csr mcause, 0xbad
|
||||||
|
write_read_csr mtval, 0xbad
|
||||||
|
write_read_csr mip, 0xbad
|
||||||
|
# write_read_csr mtinst, 0xbad # *** these appear not to be implemented in the compile step of make???
|
||||||
|
# write_read_csr mtval2, 0xbad
|
||||||
|
|
||||||
|
# Machine Configuration
|
||||||
|
# write_read_csr menvcfg, 0xbad # *** these appear not to be implemented in the compile step of make???
|
||||||
|
# write_read_csr mseccgf, 0xbad
|
||||||
|
|
||||||
|
# Machine Memory Protection
|
||||||
|
write_read_csr pmpcfg0, 0xbad
|
||||||
|
write_read_csr pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
|
||||||
|
|
||||||
|
write_read_csr pmpaddr0, 0xbad
|
||||||
|
write_read_csr pmpaddr1, 0xbad
|
||||||
|
write_read_csr pmpaddr2, 0xbad
|
||||||
|
write_read_csr pmpaddr3, 0xbad
|
||||||
|
write_read_csr pmpaddr4, 0xbad
|
||||||
|
write_read_csr pmpaddr5, 0xbad
|
||||||
|
write_read_csr pmpaddr6, 0xbad
|
||||||
|
write_read_csr pmpaddr7, 0xbad
|
||||||
|
write_read_csr pmpaddr8, 0xbad
|
||||||
|
write_read_csr pmpaddr9, 0xbad
|
||||||
|
write_read_csr pmpaddr10, 0xbad
|
||||||
|
write_read_csr pmpaddr11, 0xbad
|
||||||
|
write_read_csr pmpaddr12, 0xbad
|
||||||
|
write_read_csr pmpaddr13, 0xbad
|
||||||
|
write_read_csr pmpaddr14, 0xbad
|
||||||
|
write_read_csr pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
|
||||||
|
|
||||||
|
# Machine Counter/Timers
|
||||||
|
write_read_csr mcycle, 0xbad
|
||||||
|
write_read_csr minstret, 0xbad
|
||||||
|
write_read_csr mhpmcounter3, 0xbad
|
||||||
|
write_read_csr mhpmcounter4, 0xbad
|
||||||
|
write_read_csr mhpmcounter5, 0xbad
|
||||||
|
write_read_csr mhpmcounter6, 0xbad
|
||||||
|
write_read_csr mhpmcounter7, 0xbad
|
||||||
|
write_read_csr mhpmcounter8, 0xbad
|
||||||
|
write_read_csr mhpmcounter9, 0xbad
|
||||||
|
write_read_csr mhpmcounter10, 0xbad
|
||||||
|
write_read_csr mhpmcounter11, 0xbad
|
||||||
|
write_read_csr mhpmcounter12, 0xbad
|
||||||
|
write_read_csr mhpmcounter13, 0xbad
|
||||||
|
write_read_csr mhpmcounter14, 0xbad
|
||||||
|
write_read_csr mhpmcounter15, 0xbad
|
||||||
|
write_read_csr mhpmcounter16, 0xbad
|
||||||
|
write_read_csr mhpmcounter17, 0xbad
|
||||||
|
write_read_csr mhpmcounter18, 0xbad
|
||||||
|
write_read_csr mhpmcounter19, 0xbad
|
||||||
|
write_read_csr mhpmcounter20, 0xbad
|
||||||
|
write_read_csr mhpmcounter21, 0xbad
|
||||||
|
write_read_csr mhpmcounter22, 0xbad
|
||||||
|
write_read_csr mhpmcounter23, 0xbad
|
||||||
|
write_read_csr mhpmcounter24, 0xbad
|
||||||
|
write_read_csr mhpmcounter25, 0xbad
|
||||||
|
write_read_csr mhpmcounter26, 0xbad
|
||||||
|
write_read_csr mhpmcounter27, 0xbad
|
||||||
|
write_read_csr mhpmcounter28, 0xbad
|
||||||
|
write_read_csr mhpmcounter29, 0xbad
|
||||||
|
write_read_csr mhpmcounter30, 0xbad
|
||||||
|
write_read_csr mhpmcounter31, 0xbad
|
||||||
|
|
||||||
|
# Machine Counter Setup
|
||||||
|
write_read_csr mcountinhibit, 0xbad
|
||||||
|
write_read_csr mhpmevent3, 0xbad
|
||||||
|
write_read_csr mhpmevent4, 0xbad
|
||||||
|
write_read_csr mhpmevent5, 0xbad
|
||||||
|
write_read_csr mhpmevent6, 0xbad
|
||||||
|
write_read_csr mhpmevent7, 0xbad
|
||||||
|
write_read_csr mhpmevent8, 0xbad
|
||||||
|
write_read_csr mhpmevent9, 0xbad
|
||||||
|
write_read_csr mhpmevent10, 0xbad
|
||||||
|
write_read_csr mhpmevent11, 0xbad
|
||||||
|
write_read_csr mhpmevent12, 0xbad
|
||||||
|
write_read_csr mhpmevent13, 0xbad
|
||||||
|
write_read_csr mhpmevent14, 0xbad
|
||||||
|
write_read_csr mhpmevent15, 0xbad
|
||||||
|
write_read_csr mhpmevent16, 0xbad
|
||||||
|
write_read_csr mhpmevent17, 0xbad
|
||||||
|
write_read_csr mhpmevent18, 0xbad
|
||||||
|
write_read_csr mhpmevent19, 0xbad
|
||||||
|
write_read_csr mhpmevent20, 0xbad
|
||||||
|
write_read_csr mhpmevent21, 0xbad
|
||||||
|
write_read_csr mhpmevent22, 0xbad
|
||||||
|
write_read_csr mhpmevent23, 0xbad
|
||||||
|
write_read_csr mhpmevent24, 0xbad
|
||||||
|
write_read_csr mhpmevent25, 0xbad
|
||||||
|
write_read_csr mhpmevent26, 0xbad
|
||||||
|
write_read_csr mhpmevent27, 0xbad
|
||||||
|
write_read_csr mhpmevent28, 0xbad
|
||||||
|
write_read_csr mhpmevent29, 0xbad
|
||||||
|
write_read_csr mhpmevent30, 0xbad
|
||||||
|
write_read_csr mhpmevent31, 0xbad
|
||||||
|
|
||||||
|
END_TESTS
|
||||||
@ -0,0 +1,169 @@
|
|||||||
|
///////////////////////////////////////////
|
||||||
|
//
|
||||||
|
// WALLY-CSR-permissions
|
||||||
|
//
|
||||||
|
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||||
|
//
|
||||||
|
// Created 2022-02-05
|
||||||
|
//
|
||||||
|
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||||
|
//
|
||||||
|
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||||
|
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||||
|
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||||
|
// is furnished to do so, subject to the following conditions:
|
||||||
|
//
|
||||||
|
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||||
|
//
|
||||||
|
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||||
|
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||||
|
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||||
|
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
///////////////////////////////////////////
|
||||||
|
|
||||||
|
#include "WALLY-TEST-MACROS-64.h"
|
||||||
|
|
||||||
|
INIT_TESTS
|
||||||
|
|
||||||
|
# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode.
|
||||||
|
|
||||||
|
goto_u_mode 0x0, 0x0
|
||||||
|
|
||||||
|
# Attempt to write 0xbad to each of these CSRs and read the value back
|
||||||
|
# should result in an illegal instruction for the write and read, respectively
|
||||||
|
|
||||||
|
# Supervisor Trap Setup
|
||||||
|
write_read_csr sstatus, 0xbad
|
||||||
|
write_read_csr sie, 0xbad
|
||||||
|
write_read_csr stvec, 0xbad
|
||||||
|
write_read_csr scounteren, 0xbad
|
||||||
|
|
||||||
|
# Supervisor Configuration
|
||||||
|
# write_read_csr senvcfg, 0xbad # *** these appear not to be implemented in the compile step of make???
|
||||||
|
|
||||||
|
# Supervisor Trap Handling
|
||||||
|
write_read_csr sscratch, 0xbad
|
||||||
|
write_read_csr sepc, 0xbad
|
||||||
|
write_read_csr scause, 0xbad
|
||||||
|
write_read_csr stval, 0xbad
|
||||||
|
write_read_csr sip, 0xbad
|
||||||
|
|
||||||
|
# Supervisor Protection and Translation
|
||||||
|
write_read_csr satp, 0xbad
|
||||||
|
|
||||||
|
# Machine information Registers
|
||||||
|
write_read_csr mvendorid, 0xbad
|
||||||
|
write_read_csr marchid, 0xbad
|
||||||
|
write_read_csr mimpid, 0xbad
|
||||||
|
write_read_csr mhartid, 0xbad
|
||||||
|
# write_read_csr mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22
|
||||||
|
|
||||||
|
# Machine Trap Setup
|
||||||
|
write_read_csr mstatus, 0xbad
|
||||||
|
write_read_csr misa, 0xbad
|
||||||
|
write_read_csr medeleg, 0xbad
|
||||||
|
write_read_csr mideleg, 0xbad
|
||||||
|
write_read_csr mie, 0xbad
|
||||||
|
write_read_csr mtvec, 0xbad
|
||||||
|
write_read_csr mcounteren, 0xbad
|
||||||
|
|
||||||
|
# Machine Trap Handling
|
||||||
|
write_read_csr mscratch, 0xbad
|
||||||
|
write_read_csr mepc, 0xbad
|
||||||
|
write_read_csr mcause, 0xbad
|
||||||
|
write_read_csr mtval, 0xbad
|
||||||
|
write_read_csr mip, 0xbad
|
||||||
|
# write_read_csr mtinst, 0xbad # *** these appear not to be implemented in the compile step of make???
|
||||||
|
# write_read_csr mtval2, 0xbad
|
||||||
|
|
||||||
|
# Machine Configuration
|
||||||
|
# write_read_csr menvcfg, 0xbad # *** these appear not to be implemented in the compile step of make???
|
||||||
|
# write_read_csr mseccgf, 0xbad
|
||||||
|
|
||||||
|
# Machine Memory Protection
|
||||||
|
write_read_csr pmpcfg0, 0xbad
|
||||||
|
write_read_csr pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs
|
||||||
|
|
||||||
|
write_read_csr pmpaddr0, 0xbad
|
||||||
|
write_read_csr pmpaddr1, 0xbad
|
||||||
|
write_read_csr pmpaddr2, 0xbad
|
||||||
|
write_read_csr pmpaddr3, 0xbad
|
||||||
|
write_read_csr pmpaddr4, 0xbad
|
||||||
|
write_read_csr pmpaddr5, 0xbad
|
||||||
|
write_read_csr pmpaddr6, 0xbad
|
||||||
|
write_read_csr pmpaddr7, 0xbad
|
||||||
|
write_read_csr pmpaddr8, 0xbad
|
||||||
|
write_read_csr pmpaddr9, 0xbad
|
||||||
|
write_read_csr pmpaddr10, 0xbad
|
||||||
|
write_read_csr pmpaddr11, 0xbad
|
||||||
|
write_read_csr pmpaddr12, 0xbad
|
||||||
|
write_read_csr pmpaddr13, 0xbad
|
||||||
|
write_read_csr pmpaddr14, 0xbad
|
||||||
|
write_read_csr pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config
|
||||||
|
|
||||||
|
# Machine Counter/Timers
|
||||||
|
write_read_csr mcycle, 0xbad
|
||||||
|
write_read_csr minstret, 0xbad
|
||||||
|
write_read_csr mhpmcounter3, 0xbad
|
||||||
|
write_read_csr mhpmcounter4, 0xbad
|
||||||
|
write_read_csr mhpmcounter5, 0xbad
|
||||||
|
write_read_csr mhpmcounter6, 0xbad
|
||||||
|
write_read_csr mhpmcounter7, 0xbad
|
||||||
|
write_read_csr mhpmcounter8, 0xbad
|
||||||
|
write_read_csr mhpmcounter9, 0xbad
|
||||||
|
write_read_csr mhpmcounter10, 0xbad
|
||||||
|
write_read_csr mhpmcounter11, 0xbad
|
||||||
|
write_read_csr mhpmcounter12, 0xbad
|
||||||
|
write_read_csr mhpmcounter13, 0xbad
|
||||||
|
write_read_csr mhpmcounter14, 0xbad
|
||||||
|
write_read_csr mhpmcounter15, 0xbad
|
||||||
|
write_read_csr mhpmcounter16, 0xbad
|
||||||
|
write_read_csr mhpmcounter17, 0xbad
|
||||||
|
write_read_csr mhpmcounter18, 0xbad
|
||||||
|
write_read_csr mhpmcounter19, 0xbad
|
||||||
|
write_read_csr mhpmcounter20, 0xbad
|
||||||
|
write_read_csr mhpmcounter21, 0xbad
|
||||||
|
write_read_csr mhpmcounter22, 0xbad
|
||||||
|
write_read_csr mhpmcounter23, 0xbad
|
||||||
|
write_read_csr mhpmcounter24, 0xbad
|
||||||
|
write_read_csr mhpmcounter25, 0xbad
|
||||||
|
write_read_csr mhpmcounter26, 0xbad
|
||||||
|
write_read_csr mhpmcounter27, 0xbad
|
||||||
|
write_read_csr mhpmcounter28, 0xbad
|
||||||
|
write_read_csr mhpmcounter29, 0xbad
|
||||||
|
write_read_csr mhpmcounter30, 0xbad
|
||||||
|
write_read_csr mhpmcounter31, 0xbad
|
||||||
|
|
||||||
|
# Machine Counter Setup
|
||||||
|
write_read_csr mcountinhibit, 0xbad
|
||||||
|
write_read_csr mhpmevent3, 0xbad
|
||||||
|
write_read_csr mhpmevent4, 0xbad
|
||||||
|
write_read_csr mhpmevent5, 0xbad
|
||||||
|
write_read_csr mhpmevent6, 0xbad
|
||||||
|
write_read_csr mhpmevent7, 0xbad
|
||||||
|
write_read_csr mhpmevent8, 0xbad
|
||||||
|
write_read_csr mhpmevent9, 0xbad
|
||||||
|
write_read_csr mhpmevent10, 0xbad
|
||||||
|
write_read_csr mhpmevent11, 0xbad
|
||||||
|
write_read_csr mhpmevent12, 0xbad
|
||||||
|
write_read_csr mhpmevent13, 0xbad
|
||||||
|
write_read_csr mhpmevent14, 0xbad
|
||||||
|
write_read_csr mhpmevent15, 0xbad
|
||||||
|
write_read_csr mhpmevent16, 0xbad
|
||||||
|
write_read_csr mhpmevent17, 0xbad
|
||||||
|
write_read_csr mhpmevent18, 0xbad
|
||||||
|
write_read_csr mhpmevent19, 0xbad
|
||||||
|
write_read_csr mhpmevent20, 0xbad
|
||||||
|
write_read_csr mhpmevent21, 0xbad
|
||||||
|
write_read_csr mhpmevent22, 0xbad
|
||||||
|
write_read_csr mhpmevent23, 0xbad
|
||||||
|
write_read_csr mhpmevent24, 0xbad
|
||||||
|
write_read_csr mhpmevent25, 0xbad
|
||||||
|
write_read_csr mhpmevent26, 0xbad
|
||||||
|
write_read_csr mhpmevent27, 0xbad
|
||||||
|
write_read_csr mhpmevent28, 0xbad
|
||||||
|
write_read_csr mhpmevent29, 0xbad
|
||||||
|
write_read_csr mhpmevent30, 0xbad
|
||||||
|
write_read_csr mhpmevent31, 0xbad
|
||||||
|
|
||||||
|
END_TESTS
|
||||||
@ -72,7 +72,7 @@
|
|||||||
.8byte 0x0, 0x0018FF0C0009001F, write_pmpcfg_0 # attempt to edit only pmp5cfg (pmpcfg0[47:40]) after lockout.
|
.8byte 0x0, 0x0018FF0C0009001F, write_pmpcfg_0 # attempt to edit only pmp5cfg (pmpcfg0[47:40]) after lockout.
|
||||||
# instruction ignored, output is 0x0018900C0009001F, NOT 0x0018FF0C0009001F
|
# instruction ignored, output is 0x0018900C0009001F, NOT 0x0018FF0C0009001F
|
||||||
.8byte 0x5, 0xFFFFFFFF, write_pmpaddr_5 # attempt to edit pmpaddr5 after lockout.
|
.8byte 0x5, 0xFFFFFFFF, write_pmpaddr_5 # attempt to edit pmpaddr5 after lockout.
|
||||||
# instruction ignored, output is 0x80100300, NOT 0xFFFFFFFF
|
# instruction ignored, output is 0x200400c0, NOT 0xFFFFFFFF
|
||||||
|
|
||||||
# Test 12.3.2.2.2 Machine mode access
|
# Test 12.3.2.2.2 Machine mode access
|
||||||
|
|
||||||
|
|||||||
@ -279,29 +279,28 @@ begin_test: // label here to jump to so we dont go through the trap handler befo
|
|||||||
|
|
||||||
// Test Summary table!
|
// Test Summary table!
|
||||||
|
|
||||||
// Test Name : Description : Fault output value : Normal output values
|
// Test Name : Description : Fault output value : Normal output values
|
||||||
// ---------------------:-------------------------------------------:-------------------------------:------------------------------------------------------
|
// ---------------------:-------------------------------------------:-------------------------------------------:------------------------------------------------------
|
||||||
// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None
|
// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None
|
||||||
// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None
|
// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None
|
||||||
// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None
|
// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None
|
||||||
// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None
|
// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None
|
||||||
// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||||
// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||||
// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||||
// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||||
// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111)
|
// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111)
|
||||||
// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||||
// goto_baremetal : satp.MODE = bare metal : None : None
|
// goto_baremetal : satp.MODE = bare metal : None : None
|
||||||
// goto_sv39 : satp.MODE = sv39 : None : None
|
// goto_sv39 : satp.MODE = sv39 : None : None
|
||||||
// goto_sv48 : satp.MODE = sv48 : None : None
|
// goto_sv48 : satp.MODE = sv48 : None : None
|
||||||
// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||||
// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||||
// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||||
// write_csr : write to specified CSR : CSR value before test attempt : value written to CSR
|
// write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR
|
||||||
// read_csr : read from specified CSR : *** None? Mcause or fault? : value read back from CSR
|
// csr_r_access : test read-only permissions on CSR : 0xbad : 0x2, then 0x11
|
||||||
|
|
||||||
|
// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value, just read CSR value
|
||||||
// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value
|
|
||||||
|
|
||||||
.macro write64_test ADDR VAL
|
.macro write64_test ADDR VAL
|
||||||
// attempt to write VAL to ADDR
|
// attempt to write VAL to ADDR
|
||||||
@ -452,13 +451,14 @@ begin_test: // label here to jump to so we dont go through the trap handler befo
|
|||||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
sfence.vma x0, x0 // *** flushes global pte's as well
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
.macro write_csr CSR VAL
|
.macro write_read_csr CSR VAL
|
||||||
// attempt to write CSR with VAL *** ASSUMES RW access to CSR in whatever privilege mode is running
|
// attempt to write CSR with VAL. Note: this also tests read access to CSR
|
||||||
// Success outputs:
|
// Success outputs:
|
||||||
// value read back out from CSR after writing
|
// value read back out from CSR after writing
|
||||||
// Fault outputs:
|
// Fault outputs:
|
||||||
// The previous CSR value before write attempt
|
// The previous CSR value before write attempt
|
||||||
// *** Is there an associated mstatus? maybe 0x2???
|
// *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access
|
||||||
|
li x30, 0xbad // load bad value to be overwritten by csrr
|
||||||
li x29, \VAL
|
li x29, \VAL
|
||||||
csrw \CSR\(), x29
|
csrw \CSR\(), x29
|
||||||
csrr x30, \CSR
|
csrr x30, \CSR
|
||||||
@ -478,9 +478,9 @@ begin_test: // label here to jump to so we dont go through the trap handler befo
|
|||||||
csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR
|
csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR
|
||||||
csrr x30, \CSR
|
csrr x30, \CSR
|
||||||
bne x30, x29, 1f // 1f represents write_access
|
bne x30, x29, 1f // 1f represents write_access
|
||||||
li x30, 0x11 // Write succeeded, violating read only permissions.
|
li x30, 0x11 // Write failed, confirming read only permissions.
|
||||||
j 2f // j r_access_end
|
j 2f // j r_access_end
|
||||||
1: // w_access (test failed)
|
1: // w_access (write succeeded, violating read-only)
|
||||||
li x30, 0xBAD
|
li x30, 0xBAD
|
||||||
2: // r_access end
|
2: // r_access end
|
||||||
sd x30, 0(x6)
|
sd x30, 0(x6)
|
||||||
|
|||||||
@ -25,7 +25,7 @@
|
|||||||
|
|
||||||
INIT_TESTS
|
INIT_TESTS
|
||||||
|
|
||||||
// Test 5.2.3.1: tersting Read-only access to Machine info CSRs
|
// Test 5.2.3.1: testing Read-only access to Machine info CSRs
|
||||||
|
|
||||||
csr_r_access mvendorid
|
csr_r_access mvendorid
|
||||||
csr_r_access marchid
|
csr_r_access marchid
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user