diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 13ceeef3b..43e34bb76 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -88,14 +88,14 @@ for test in tests32ic: grepstr="All tests ran without failures") configs.append(tc) -tests32e = ["wally32e"] -for test in tests32e: - tc = TestCase( - name=test, - variant="rv32e", - cmd="vsim > {} -c < {} -c < /dev/null + # KMG: changed diff snippet to a grep that will strip comments with '//' and '#' out of the reference file + diff --ignore-case --ignore-trailing-space --strip-trailing-cr <(grep -o '^[^//#]*' ${ref}) ${sig} &> /dev/null if [ $? == 0 ] then echo -e "\e[32m ... OK \e[39m" diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include b/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include index 35ca54187..ae84be741 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include +++ b/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include @@ -63,8 +63,9 @@ copy: $(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!) $(info <<<<<<<<<<<<<<<<<<<<<<<<<<<< COPYING REFERENCES WITHOUT SIMULATING >>>>>>>>>>>>>>>>>>>>>>>>>>>>) $(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!) - $(V) echo "Copying References without simulating" - $(V) for test in $(target_tests_nosim); do cp $(ref_dir)/$$test.reference_output $(work_dir_isa)/$$test.signature.output; done + $(V) echo "Copying References without simulating for the following tests:" + $(V) echo $(target_tests_nosim) + $(V) for test in $(target_tests_nosim); do grep -o '^[^//#]*' $(ref_dir)/$$test.reference_output > $(work_dir_isa)/$$test.signature.output; done compile: $(combined_elf) run: $(target_log) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag index 03ddfcf65..eda625075 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag @@ -28,48 +28,11 @@ # Description: Makefrag for RV32I architectural tests rv32i_sc_tests = \ - E-add-01 \ - E-addi-01 \ - E-and-01 \ - E-andi-01 \ - E-auipc-01 \ - E-beq-01 \ - E-bge-01 \ - E-bgeu-01 \ - E-blt-01 \ - E-bltu-01 \ - E-bne-01 \ - E-jal-01 \ - E-jalr-01 \ - E-lb-align-01 \ - E-lbu-align-01 \ - E-lh-align-01 \ - E-lhu-align-01 \ - E-lui-01 \ - E-lw-align-01 \ - E-or-01 \ - E-ori-01 \ - E-sb-align-01 \ - E-sh-align-01 \ - E-sll-01 \ - E-slli-01 \ - E-slt-01 \ - E-slti-01 \ - E-sltiu-01 \ - E-sltu-01 \ - E-sra-01 \ - E-srai-01 \ - E-srl-01 \ - E-srli-01 \ - E-sub-01 \ - E-sw-align-01 \ - E-xor-01 \ - E-xori-01 \ WALLY-ADD \ - WALLY-SUB \ - WALLY-SLT \ + WALLY-SLT \ WALLY-SLTU \ - WALLY-XOR + WALLY-SUB \ + WALLY-XOR rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index aa30cdc79..e8c000283 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -31,7 +31,9 @@ rv64i_sc_tests = \ WALLY-MMU-SV39 \ WALLY-MMU-SV48 \ WALLY-PMP \ - WALLY-minfo-01 + WALLY-minfo-01 \ + WALLY-CSR-permission-s-01 \ + WALLY-CSR-permission-u-01 target_tests_nosim = WALLY-PMA \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-s-01.reference_output new file mode 100644 index 000000000..811bfe7ca --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-s-01.reference_output @@ -0,0 +1,1024 @@ +0000000b # Test 5.2.3.6: ecall from going to S mode from M mode +00000000 +00000002 # S mode write to mvendorid with illegal instruction +00000000 +00000002 # S mode read from mvendorid with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to marchid with illegal instruction +00000000 +00000002 # S mode read from marchid with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mimpid with illegal instruction +00000000 +00000002 # S mode read from mimpid with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhartid with illegal instruction +00000000 +00000002 # S mode read from mhartid with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mstatus with illegal instruction +00000000 +00000002 # S mode read from mstatus with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to misa with illegal instruction +00000000 +00000002 # S mode read from misa with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to medeleg with illegal instruction +00000000 +00000002 # S mode read from medeleg with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mideleg with illegal instruction +00000000 +00000002 # S mode read from mideleg with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mie with illegal instruction +00000000 +00000002 # S mode read from mie with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mtvec with illegal instruction +00000000 +00000002 # S mode read from mtvec with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mcounteren with illegal instruction +00000000 +00000002 # S mode read from mcounteren with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mscratch with illegal instruction +00000000 +00000002 # S mode read from mscratch with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mepc with illegal instruction +00000000 +00000002 # S mode read from mepc with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mcause with illegal instruction +00000000 +00000002 # S mode read from mcause with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mtval with illegal instruction +00000000 +00000002 # S mode read from mtval with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mip with illegal instruction +00000000 +00000002 # S mode read from mip with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpcfg0 with illegal instruction +00000000 +00000002 # S mode read from pmpcfg0 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpcfg2 with illegal instruction +00000000 +00000002 # S mode read from pmpcfg2 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr0 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr0 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr1 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr1 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr2 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr2 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr3 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr4 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr5 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr6 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr7 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr8 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr9 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr10 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr11 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr12 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr13 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr14 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr15 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mcycle with illegal instruction +00000000 +00000002 # S mode read from mcycle with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to minstret with illegal instruction +00000000 +00000002 # S mode read from minstret with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter3 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter4 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter5 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter6 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter7 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter8 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter9 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter10 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter11 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter12 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter13 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter14 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter15 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter16 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter16 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter17 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter17 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter18 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter18 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter19 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter19 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter20 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter20 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter21 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter21 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter22 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter22 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter23 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter23 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter24 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter24 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter25 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter25 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter26 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter26 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter27 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter27 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter28 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter28 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter29 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter29 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter30 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter30 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter31 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter31 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mcountinhibit with illegal instruction +00000000 +00000002 # S mode read from mcountinhibit with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent3 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent4 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent5 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent6 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent7 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent8 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent9 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent10 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent11 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent12 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent13 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent14 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent15 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent16 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent16 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent17 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent17 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent18 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent18 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent19 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent19 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent20 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent20 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent21 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent21 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent22 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent22 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent23 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent23 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent24 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent24 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent25 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent25 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent26 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent26 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent27 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent27 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent28 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent28 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent29 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent29 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent30 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent30 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent31 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent31 with illegal instruction +00000000 +00000bad +00000000 +00000009 # ecall from terminating tess from S mode +00000000 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-u-01.reference_output new file mode 100644 index 000000000..c8cd62ab1 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-u-01.reference_output @@ -0,0 +1,1024 @@ +0000000b # Test 5.2.3.6: ecall from going to U mode from M mode +00000000 +00000002 # U mode write to sstatus with illegal instruction +00000000 +00000002 # U mode read from sstatus with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to sie with illegal instruction +00000000 +00000002 # U mode read from sie with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to stvec with illegal instruction +00000000 +00000002 # U mode read from stvec with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to scounteren with illegal instruction +00000000 +00000002 # U mode read from scounteren with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to sscratch with illegal instruction +00000000 +00000002 # U mode read from sscratch with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to sepc with illegal instruction +00000000 +00000002 # U mode read from sepc with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to scause with illegal instruction +00000000 +00000002 # U mode read from scause with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to stval with illegal instruction +00000000 +00000002 # U mode read from stval with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to sip with illegal instruction +00000000 +00000002 # U mode read from sip with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to satp with illegal instruction +00000000 +00000002 # U mode read from satp with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mvendorid with illegal instruction +00000000 +00000002 # U mode read from mvendorid with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to marchid with illegal instruction +00000000 +00000002 # U mode read from marchid with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mimpid with illegal instruction +00000000 +00000002 # U mode read from mimpid with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhartid with illegal instruction +00000000 +00000002 # U mode read from mhartid with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mstatus with illegal instruction +00000000 +00000002 # U mode read from mstatus with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to misa with illegal instruction +00000000 +00000002 # U mode read from misa with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to medeleg with illegal instruction +00000000 +00000002 # U mode read from medeleg with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mideleg with illegal instruction +00000000 +00000002 # U mode read from mideleg with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mie with illegal instruction +00000000 +00000002 # U mode read from mie with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mtvec with illegal instruction +00000000 +00000002 # U mode read from mtvec with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mcounteren with illegal instruction +00000000 +00000002 # U mode read from mcounteren with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mscratch with illegal instruction +00000000 +00000002 # U mode read from mscratch with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mepc with illegal instruction +00000000 +00000002 # U mode read from mepc with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mcause with illegal instruction +00000000 +00000002 # U mode read from mcause with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mtval with illegal instruction +00000000 +00000002 # U mode read from mtval with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mip with illegal instruction +00000000 +00000002 # U mode read from mip with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpcfg0 with illegal instruction +00000000 +00000002 # U mode read from pmpcfg0 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpcfg2 with illegal instruction +00000000 +00000002 # U mode read from pmpcfg2 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr0 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr0 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr1 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr1 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr2 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr2 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr3 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr4 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr5 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr6 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr7 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr8 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr9 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr10 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr11 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr12 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr13 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr14 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr15 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mcycle with illegal instruction +00000000 +00000002 # U mode read from mcycle with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to minstret with illegal instruction +00000000 +00000002 # U mode read from minstret with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter3 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter4 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter5 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter6 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter7 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter8 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter9 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter10 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter11 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter12 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter13 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter14 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter15 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter16 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter16 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter17 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter17 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter18 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter18 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter19 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter19 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter20 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter20 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter21 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter21 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter22 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter22 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter23 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter23 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter24 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter24 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter25 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter25 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter26 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter26 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter27 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter27 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter28 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter28 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter29 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter29 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter30 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter30 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter31 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter31 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mcountinhibit with illegal instruction +00000000 +00000002 # U mode read from mcountinhibit with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent3 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent4 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent5 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent6 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent7 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent8 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent9 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent10 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent11 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent12 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent13 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent14 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent15 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent16 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent16 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent17 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent17 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent18 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent18 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent19 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent19 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent20 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent20 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent21 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent21 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent22 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent22 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent23 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent23 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent24 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent24 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent25 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent25 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent26 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent26 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent27 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent27 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent28 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent28 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent29 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent29 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent30 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent30 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent31 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent31 with illegal instruction +00000000 +00000bad +00000000 +00000008 # ecall from terminating tests in U mode +00000000 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output index 492379dee..b0f6ca4c7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output @@ -1,104 +1,104 @@ -0000000b +0000000b # Test 12.3.1.1.3: ecall from going to S mode from M mode 00000000 -beef0000 +beef0000 # 7 read test successes 0000dead -beef0055 +beef0055 # read 2 0880dead -beef0033 +beef0033 # read 3 0990dead -beef0077 +beef0077 # read 4 0110dead -beef0099 +beef0099 # read 5 0220dead -beef0440 +beef0440 # read 6 0330dead -beef0bb0 +beef0bb0 # read 7 0440dead -beef0000 +beef0000 # Test 12.3.1.1.4: 3 read test successes 0000dead -beef0055 +beef0055 # read 2 0880dead -beef0099 +beef0099 # read 3 0220dead -0000000d +0000000d # Test 12.3.1.2.1: 2 read tests with page fault 00000000 00000bad 00000000 -0000000d +0000000d # read 2 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.2.2: read test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.2.3: write test with page fault 00000000 -0000000d +0000000d # Test 12.3.1.2.4: read test with page fault 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.2.5: 2 read tests with page faults 00000000 00000bad 00000000 -0000000d +0000000d # read 2 00000000 00000bad 00000000 -00000111 +00000111 # Test 12.3.1.3.1: execute test success 00000000 -00000009 +00000009 # ecall from going to U mode from S mode 00000000 -0000000d +0000000d # read test with page fault 00000000 00000bad 00000000 -0000000c +0000000c # execute test with page fault 00000000 00000bad 00000000 -beef0033 +beef0033 # Test 12.3.1.3.2: read test success 0990dead -00000008 +00000008 # ecall from going to S mode from U mode 00000000 -beef0077 +beef0077 # read test success 0110dead -0000000c +0000000c # execute test with page fault 00000000 00000bad 00000000 -0000000d +0000000d # read test with page fault 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.3.3: read test with page fault 00000000 00000bad 00000000 -beef0440 +beef0440 # read test success 0330dead -beef0110 +beef0110 # Test 12.3.1.3.4: read test success 0440dead -0000000f +0000000f # write test with page fault 00000000 -0000000c +0000000c # Test 12.3.1.3.5: execute test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.3.6: write test with page fault 00000000 -0000000d +0000000d # read test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.3.7: write test with page fault 00000000 -beef0bb0 +beef0bb0 # read test success 0440dead -00000009 +00000009 # ecall from test termination from S mode 00000000 -deadbeef +deadbeef # rest of the output space deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output index 68a13c253..1d4ff8e33 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output @@ -1,112 +1,112 @@ -0000000b +0000000b # Test 12.3.1.1.3: ecall from going to S mode from M mode 00000000 -beef0cc0 +beef0cc0 # 8 read test successes 0ee0dead -beef0000 +beef0000 # read 2 0000dead -beef0055 +beef0055 # read 3 0880dead -beef0033 +beef0033 # read 4 0990dead -beef0077 +beef0077 # read 5 0110dead -beef0099 +beef0099 # read 6 0220dead -beef0440 +beef0440 # read 7 0330dead -beef0bb0 +beef0bb0 # read 8 0440dead -beef0cc0 +beef0cc0 # Test 12.3.1.1.4: 4 read test successes 0ee0dead -beef0000 +beef0000 # read 2 0000dead -beef0055 +beef0055 # read 3 0880dead -beef0099 +beef0099 # read 4 0220dead -0000000d +0000000d # Test 12.3.1.2.1: 2 read tests with page fault 00000000 00000bad 00000000 -0000000d +0000000d # read 2 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.2.2: read test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.2.3: write test with page fault 00000000 -0000000d +0000000d # Test 12.3.1.2.4: read test with page fault 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.2.5: 3 read tests with page fault 00000000 00000bad 00000000 -0000000d +0000000d # read 2 00000000 00000bad 00000000 -0000000d +0000000d # read 3 00000000 00000bad 00000000 -00000111 +00000111 # Test 12.3.1.3.1: Execute test success 00000000 -00000009 +00000009 # ecall from going to U mode from S mode 00000000 -0000000d +0000000d # read test with page fault 00000000 00000bad 00000000 -0000000c +0000000c # execute test with page fault 00000000 00000bad 00000000 -beef0033 +beef0033 # Test 12.3.1.3.2: read test success 0990dead -00000008 +00000008 # ecall from going to S mode from U mode 00000000 -beef0077 +beef0077 # read test success 0110dead -0000000c +0000000c # execute test with page fault 00000000 00000bad 00000000 -0000000d +0000000d # read test with page fault` 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.3.3: read test with page fault 00000000 00000bad 00000000 -beef0440 +beef0440 # read test success 0330dead -beef0110 +beef0110 # Test 12.3.1.3.4: read test success 0440dead -0000000f +0000000f # write test with page fault 00000000 -0000000c +0000000c # Test 12.3.1.3.5: executable test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.3.6: write test with page fault 00000000 -0000000d +0000000d # read test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.3.7: write test with page fault 00000000 -beef0bb0 +beef0bb0 # read test success 0440dead -00000009 +00000009 # ecall from test termination in S mode. 00000000 -deadbeef +deadbeef # rest of the output space deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output index 7ba4cff92..c8a68e8e2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output @@ -1,148 +1,148 @@ -beef00b4 -0000dead -beef00b5 +beef00b4 # Test 12.3.2.1: read 64 bits success in CLINT +0000dead # all of these read successes are also confirming successful writes +beef00b5 # read 32 bits success in CLINT (sign extended) ffffffff -000000b6 +000000b6 # read 16 bits success in CLINT 00000000 -ffffffb7 +ffffffb7 # read 8 bits success in CLINT (sign extended) ffffffff -00000001 +00000001 # execute test with access fault in CLINT 00000000 00000bad 00000000 -00000007 +00000007 # write 64 bits with access fault in PLIC 00000000 -00000005 +00000005 # read 64 bits with access fault in PLIC 00000000 00000bad 00000000 -00000002 +00000002 # read 32 bits success in PLIC (confriming 32 bit write) 00000000 -00000007 +00000007 # write 16 bits with access fault in PLIC 00000000 -00000005 +00000005 # read 16 bits with access fault in PLIC 00000000 00000bad 00000000 -00000007 +00000007 # write 8 bits with access fault in PLIC 00000000 -00000005 +00000005 # read 8 bits with access fault in PLIC 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault in PLIC 00000000 00000bad 00000000 -00000007 +00000007 # write 64 bits with access fault in UART 00000000 -00000005 +00000005 # read 64 bits with access fault in UART 00000000 00000bad 00000000 -00000007 +00000007 # write 32 bits with access fault in UART 00000000 -00000005 +00000005 # read 32 bits with access fault in UART 00000000 00000bad 00000000 -00000007 +00000007 # write 16 bits with access fault in UART 00000000 -00000005 +00000005 # read 16 bits with access fault in UART 00000000 00000bad 00000000 -ffffffbf +ffffffbf # read 8 bits success in UART (confirming 8 bit write) ffffffff -00000001 +00000001 # execute test with access fault in UART 00000000 00000bad 00000000 -00000007 +00000007 # write 64 bits with access fault in GPIO 00000000 -00000005 +00000005 # read 64 bits with access fault in GPIO 00000000 00000bad 00000000 -beef00c1 +beef00c1 # read 32 bits success in GPIO (confirming 32 bit write) ffffffff -00000007 +00000007 # write 16 bits with access fault in GPIO 00000000 -00000005 +00000005 # read 16 bits with access fault in GPIO 00000000 00000bad 00000000 -00000007 +00000007 # write 8 bits with access fault in GPIO 00000000 -00000005 +00000005 # read 8 bits with access fault in GPIO 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault in GPIO 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault in random memory location 00000000 -00000005 +00000005 # read test with access fault in random memory location 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault in random memory location 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault just after BOOTROM 00000000 -00000005 +00000005 # read test with access fault just after BOOTROM 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault just after BOOTROM 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault just after CLINT 00000000 -00000005 +00000005 # read test with access fault just after CLINT 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault just after CLINT 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault just after PLIC 00000000 -00000005 +00000005 # read test with access fault just after PLIC 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault just after PLIC 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault just after UART 00000000 -00000005 +00000005 # read test with access fault just after UART 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault just after UART 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault just after GPIO 00000000 -00000005 +00000005 # read test with access fault just after GPIO 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault just after GPIO 00000000 00000bad 00000000 -0000000b +0000000b # ecall from terminating tests in M mode 00000000 deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output index 931f8a160..ea5a0cb18 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output @@ -1,58 +1,58 @@ -0fffffff +0fffffff # Test 12.3.2.2.1: writeback of value written to PMPADDR0 +00000000 +20040000 # writeback of value written to PMPADDR1 00000000 -20040000 +2004003f # writeback of value written to PMPADDR2 00000000 -2004003f +20040080 # writeback of value written to PMPADDR3 00000000 -20040080 +20040084 # writeback of value written to PMPADDR4 00000000 -20040084 +200400c0 # writeback of value written to PMPADDR5 00000000 -200400c0 +2004013f # writeback of value written to PMPADDR6 00000000 -2004013f +2fffffff # writeback of value written to PMPADDR15 00000000 -2fffffff -00000000 -0009001f +0009001f # writeback of value written to PMPCFG0 0018900c -00000000 +00000000 # writeback of value written to PMPCFG2 1f000000 -0009001f +0009001f # old value of PMPCFG0 after failed write to locked out region 0018900c -200400c0 +200400c0 # old value of PMPADDR5 after failed write to locked out region 00000000 -00000005 +00000005 # Test 12.3.2.2.2: read test with access fault to region with L=1, R=0 00000000 00000bad 00000000 -00600dbb +00600dbb # read test success from region with L=X=W=R=0 00000000 -0000000b +0000000b # Test 12.3.2.2.3: ecall from going to S mode from M mode 00000000 -00600d15 +00600d15 # read test success from RW range (confirming previous write) 00000000 -00600d02 +00600d02 # read test success from outside the edge of a read only range 00000000 -00600d12 +00600d12 # read test success from outside the other edge of a read only range 00000000 -00000007 +00000007 # write test with access fault in read only range 00000000 -00600daa +00600daa # read success from read only range 00000000 -00000007 +00000007 # write test with access fault in no-access range 00000000 -00000005 +00000005 # read test with access fault in no-access range 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault in no-execute range 00000000 00000bad 00000000 -00000111 +00000111 # execute sucess when X=1 00000000 -00000009 +00000009 # ecall from terminating tests in S mode 00000000 deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output index 880d5dc82..e37c37626 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output @@ -1,20 +1,20 @@ -00000002 +00000002 # Test 5.2.3.1: write to read-only CSR failed with illegal instruction 00000000 -00000011 +00000011 # confirm read-only permissions of mvendorid 00000000 -00000002 +00000002 # write to read-only CSR failed with illegal instruction 00000000 -00000011 +00000011 # confirm read-only permissions of marchid 00000000 -00000002 +00000002 # write to read-only CSR failed with illegal instruction 00000000 -00000011 +00000011 # confirm read-only permissions of mimpid 00000000 -00000002 +00000002 # write to read-only CSR failed with illegal instruction 00000000 -00000011 +00000011 # confirm read-only permissions of mhartid 00000000 -0000000b +0000000b # ecall from terminating tests in M mode 00000000 deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S new file mode 100644 index 000000000..ce1069834 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S @@ -0,0 +1,153 @@ +/////////////////////////////////////////// +// +// WALLY-CSR-permissions +// +// Author: Kip Macsai-Goren +// +// Created 2022-02-05 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-MACROS-64.h" + +INIT_TESTS + +# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode. + +# *** several of these appear not to be implemented in the assembler? +# I get "assembler messages: error: unkown CSR" with many of them. + +goto_s_mode 0x0, 0x0 + +# Attempt to write 0xbad to each of these CSRs and read the value back +# should result in an illegal instruction for the write and read, respectively + +# Machine information Registers +write_read_csr mvendorid, 0xbad +write_read_csr marchid, 0xbad +write_read_csr mimpid, 0xbad +write_read_csr mhartid, 0xbad +# write_read_csr mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 + +# Machine Trap Setup +write_read_csr mstatus, 0xbad +write_read_csr misa, 0xbad +write_read_csr medeleg, 0xbad +write_read_csr mideleg, 0xbad +write_read_csr mie, 0xbad +write_read_csr mtvec, 0xbad +write_read_csr mcounteren, 0xbad + +# Machine Trap Handling +write_read_csr mscratch, 0xbad +write_read_csr mepc, 0xbad +write_read_csr mcause, 0xbad +write_read_csr mtval, 0xbad +write_read_csr mip, 0xbad +# write_read_csr mtinst, 0xbad # *** these appear not to be implemented in the compile step of make??? +# write_read_csr mtval2, 0xbad + +# Machine Configuration +# write_read_csr menvcfg, 0xbad # *** these appear not to be implemented in the compile step of make??? +# write_read_csr mseccgf, 0xbad + +# Machine Memory Protection +write_read_csr pmpcfg0, 0xbad +write_read_csr pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs + +write_read_csr pmpaddr0, 0xbad +write_read_csr pmpaddr1, 0xbad +write_read_csr pmpaddr2, 0xbad +write_read_csr pmpaddr3, 0xbad +write_read_csr pmpaddr4, 0xbad +write_read_csr pmpaddr5, 0xbad +write_read_csr pmpaddr6, 0xbad +write_read_csr pmpaddr7, 0xbad +write_read_csr pmpaddr8, 0xbad +write_read_csr pmpaddr9, 0xbad +write_read_csr pmpaddr10, 0xbad +write_read_csr pmpaddr11, 0xbad +write_read_csr pmpaddr12, 0xbad +write_read_csr pmpaddr13, 0xbad +write_read_csr pmpaddr14, 0xbad +write_read_csr pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config + +# Machine Counter/Timers +write_read_csr mcycle, 0xbad +write_read_csr minstret, 0xbad +write_read_csr mhpmcounter3, 0xbad +write_read_csr mhpmcounter4, 0xbad +write_read_csr mhpmcounter5, 0xbad +write_read_csr mhpmcounter6, 0xbad +write_read_csr mhpmcounter7, 0xbad +write_read_csr mhpmcounter8, 0xbad +write_read_csr mhpmcounter9, 0xbad +write_read_csr mhpmcounter10, 0xbad +write_read_csr mhpmcounter11, 0xbad +write_read_csr mhpmcounter12, 0xbad +write_read_csr mhpmcounter13, 0xbad +write_read_csr mhpmcounter14, 0xbad +write_read_csr mhpmcounter15, 0xbad +write_read_csr mhpmcounter16, 0xbad +write_read_csr mhpmcounter17, 0xbad +write_read_csr mhpmcounter18, 0xbad +write_read_csr mhpmcounter19, 0xbad +write_read_csr mhpmcounter20, 0xbad +write_read_csr mhpmcounter21, 0xbad +write_read_csr mhpmcounter22, 0xbad +write_read_csr mhpmcounter23, 0xbad +write_read_csr mhpmcounter24, 0xbad +write_read_csr mhpmcounter25, 0xbad +write_read_csr mhpmcounter26, 0xbad +write_read_csr mhpmcounter27, 0xbad +write_read_csr mhpmcounter28, 0xbad +write_read_csr mhpmcounter29, 0xbad +write_read_csr mhpmcounter30, 0xbad +write_read_csr mhpmcounter31, 0xbad + +# Machine Counter Setup +write_read_csr mcountinhibit, 0xbad +write_read_csr mhpmevent3, 0xbad +write_read_csr mhpmevent4, 0xbad +write_read_csr mhpmevent5, 0xbad +write_read_csr mhpmevent6, 0xbad +write_read_csr mhpmevent7, 0xbad +write_read_csr mhpmevent8, 0xbad +write_read_csr mhpmevent9, 0xbad +write_read_csr mhpmevent10, 0xbad +write_read_csr mhpmevent11, 0xbad +write_read_csr mhpmevent12, 0xbad +write_read_csr mhpmevent13, 0xbad +write_read_csr mhpmevent14, 0xbad +write_read_csr mhpmevent15, 0xbad +write_read_csr mhpmevent16, 0xbad +write_read_csr mhpmevent17, 0xbad +write_read_csr mhpmevent18, 0xbad +write_read_csr mhpmevent19, 0xbad +write_read_csr mhpmevent20, 0xbad +write_read_csr mhpmevent21, 0xbad +write_read_csr mhpmevent22, 0xbad +write_read_csr mhpmevent23, 0xbad +write_read_csr mhpmevent24, 0xbad +write_read_csr mhpmevent25, 0xbad +write_read_csr mhpmevent26, 0xbad +write_read_csr mhpmevent27, 0xbad +write_read_csr mhpmevent28, 0xbad +write_read_csr mhpmevent29, 0xbad +write_read_csr mhpmevent30, 0xbad +write_read_csr mhpmevent31, 0xbad + +END_TESTS \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S new file mode 100644 index 000000000..d7984d7f6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S @@ -0,0 +1,169 @@ +/////////////////////////////////////////// +// +// WALLY-CSR-permissions +// +// Author: Kip Macsai-Goren +// +// Created 2022-02-05 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-MACROS-64.h" + +INIT_TESTS + +# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode. + +goto_u_mode 0x0, 0x0 + +# Attempt to write 0xbad to each of these CSRs and read the value back +# should result in an illegal instruction for the write and read, respectively + +# Supervisor Trap Setup +write_read_csr sstatus, 0xbad +write_read_csr sie, 0xbad +write_read_csr stvec, 0xbad +write_read_csr scounteren, 0xbad + +# Supervisor Configuration +# write_read_csr senvcfg, 0xbad # *** these appear not to be implemented in the compile step of make??? + +# Supervisor Trap Handling +write_read_csr sscratch, 0xbad +write_read_csr sepc, 0xbad +write_read_csr scause, 0xbad +write_read_csr stval, 0xbad +write_read_csr sip, 0xbad + +# Supervisor Protection and Translation +write_read_csr satp, 0xbad + +# Machine information Registers +write_read_csr mvendorid, 0xbad +write_read_csr marchid, 0xbad +write_read_csr mimpid, 0xbad +write_read_csr mhartid, 0xbad +# write_read_csr mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 + +# Machine Trap Setup +write_read_csr mstatus, 0xbad +write_read_csr misa, 0xbad +write_read_csr medeleg, 0xbad +write_read_csr mideleg, 0xbad +write_read_csr mie, 0xbad +write_read_csr mtvec, 0xbad +write_read_csr mcounteren, 0xbad + +# Machine Trap Handling +write_read_csr mscratch, 0xbad +write_read_csr mepc, 0xbad +write_read_csr mcause, 0xbad +write_read_csr mtval, 0xbad +write_read_csr mip, 0xbad +# write_read_csr mtinst, 0xbad # *** these appear not to be implemented in the compile step of make??? +# write_read_csr mtval2, 0xbad + +# Machine Configuration +# write_read_csr menvcfg, 0xbad # *** these appear not to be implemented in the compile step of make??? +# write_read_csr mseccgf, 0xbad + +# Machine Memory Protection +write_read_csr pmpcfg0, 0xbad +write_read_csr pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs + +write_read_csr pmpaddr0, 0xbad +write_read_csr pmpaddr1, 0xbad +write_read_csr pmpaddr2, 0xbad +write_read_csr pmpaddr3, 0xbad +write_read_csr pmpaddr4, 0xbad +write_read_csr pmpaddr5, 0xbad +write_read_csr pmpaddr6, 0xbad +write_read_csr pmpaddr7, 0xbad +write_read_csr pmpaddr8, 0xbad +write_read_csr pmpaddr9, 0xbad +write_read_csr pmpaddr10, 0xbad +write_read_csr pmpaddr11, 0xbad +write_read_csr pmpaddr12, 0xbad +write_read_csr pmpaddr13, 0xbad +write_read_csr pmpaddr14, 0xbad +write_read_csr pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config + +# Machine Counter/Timers +write_read_csr mcycle, 0xbad +write_read_csr minstret, 0xbad +write_read_csr mhpmcounter3, 0xbad +write_read_csr mhpmcounter4, 0xbad +write_read_csr mhpmcounter5, 0xbad +write_read_csr mhpmcounter6, 0xbad +write_read_csr mhpmcounter7, 0xbad +write_read_csr mhpmcounter8, 0xbad +write_read_csr mhpmcounter9, 0xbad +write_read_csr mhpmcounter10, 0xbad +write_read_csr mhpmcounter11, 0xbad +write_read_csr mhpmcounter12, 0xbad +write_read_csr mhpmcounter13, 0xbad +write_read_csr mhpmcounter14, 0xbad +write_read_csr mhpmcounter15, 0xbad +write_read_csr mhpmcounter16, 0xbad +write_read_csr mhpmcounter17, 0xbad +write_read_csr mhpmcounter18, 0xbad +write_read_csr mhpmcounter19, 0xbad +write_read_csr mhpmcounter20, 0xbad +write_read_csr mhpmcounter21, 0xbad +write_read_csr mhpmcounter22, 0xbad +write_read_csr mhpmcounter23, 0xbad +write_read_csr mhpmcounter24, 0xbad +write_read_csr mhpmcounter25, 0xbad +write_read_csr mhpmcounter26, 0xbad +write_read_csr mhpmcounter27, 0xbad +write_read_csr mhpmcounter28, 0xbad +write_read_csr mhpmcounter29, 0xbad +write_read_csr mhpmcounter30, 0xbad +write_read_csr mhpmcounter31, 0xbad + +# Machine Counter Setup +write_read_csr mcountinhibit, 0xbad +write_read_csr mhpmevent3, 0xbad +write_read_csr mhpmevent4, 0xbad +write_read_csr mhpmevent5, 0xbad +write_read_csr mhpmevent6, 0xbad +write_read_csr mhpmevent7, 0xbad +write_read_csr mhpmevent8, 0xbad +write_read_csr mhpmevent9, 0xbad +write_read_csr mhpmevent10, 0xbad +write_read_csr mhpmevent11, 0xbad +write_read_csr mhpmevent12, 0xbad +write_read_csr mhpmevent13, 0xbad +write_read_csr mhpmevent14, 0xbad +write_read_csr mhpmevent15, 0xbad +write_read_csr mhpmevent16, 0xbad +write_read_csr mhpmevent17, 0xbad +write_read_csr mhpmevent18, 0xbad +write_read_csr mhpmevent19, 0xbad +write_read_csr mhpmevent20, 0xbad +write_read_csr mhpmevent21, 0xbad +write_read_csr mhpmevent22, 0xbad +write_read_csr mhpmevent23, 0xbad +write_read_csr mhpmevent24, 0xbad +write_read_csr mhpmevent25, 0xbad +write_read_csr mhpmevent26, 0xbad +write_read_csr mhpmevent27, 0xbad +write_read_csr mhpmevent28, 0xbad +write_read_csr mhpmevent29, 0xbad +write_read_csr mhpmevent30, 0xbad +write_read_csr mhpmevent31, 0xbad + +END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S index 226c93984..5c894081c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S @@ -72,7 +72,7 @@ .8byte 0x0, 0x0018FF0C0009001F, write_pmpcfg_0 # attempt to edit only pmp5cfg (pmpcfg0[47:40]) after lockout. # instruction ignored, output is 0x0018900C0009001F, NOT 0x0018FF0C0009001F .8byte 0x5, 0xFFFFFFFF, write_pmpaddr_5 # attempt to edit pmpaddr5 after lockout. -# instruction ignored, output is 0x80100300, NOT 0xFFFFFFFF +# instruction ignored, output is 0x200400c0, NOT 0xFFFFFFFF # Test 12.3.2.2.2 Machine mode access diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h index a044f737c..de54815e8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h @@ -279,29 +279,28 @@ begin_test: // label here to jump to so we dont go through the trap handler befo // Test Summary table! -// Test Name : Description : Fault output value : Normal output values -// ---------------------:-------------------------------------------:-------------------------------:------------------------------------------------------ -// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None -// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None -// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None -// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None -// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111) -// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// goto_baremetal : satp.MODE = bare metal : None : None -// goto_sv39 : satp.MODE = sv39 : None : None -// goto_sv48 : satp.MODE = sv48 : None : None -// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// write_csr : write to specified CSR : CSR value before test attempt : value written to CSR -// read_csr : read from specified CSR : *** None? Mcause or fault? : value read back from CSR +// Test Name : Description : Fault output value : Normal output values +// ---------------------:-------------------------------------------:-------------------------------------------:------------------------------------------------------ +// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None +// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None +// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None +// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None +// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111) +// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_baremetal : satp.MODE = bare metal : None : None +// goto_sv39 : satp.MODE = sv39 : None : None +// goto_sv48 : satp.MODE = sv48 : None : None +// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR +// csr_r_access : test read-only permissions on CSR : 0xbad : 0x2, then 0x11 - -// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value +// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value, just read CSR value .macro write64_test ADDR VAL // attempt to write VAL to ADDR @@ -452,13 +451,14 @@ begin_test: // label here to jump to so we dont go through the trap handler befo sfence.vma x0, x0 // *** flushes global pte's as well .endm -.macro write_csr CSR VAL - // attempt to write CSR with VAL *** ASSUMES RW access to CSR in whatever privilege mode is running +.macro write_read_csr CSR VAL + // attempt to write CSR with VAL. Note: this also tests read access to CSR // Success outputs: // value read back out from CSR after writing // Fault outputs: // The previous CSR value before write attempt - // *** Is there an associated mstatus? maybe 0x2??? + // *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access + li x30, 0xbad // load bad value to be overwritten by csrr li x29, \VAL csrw \CSR\(), x29 csrr x30, \CSR @@ -478,9 +478,9 @@ begin_test: // label here to jump to so we dont go through the trap handler befo csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR csrr x30, \CSR bne x30, x29, 1f // 1f represents write_access - li x30, 0x11 // Write succeeded, violating read only permissions. + li x30, 0x11 // Write failed, confirming read only permissions. j 2f // j r_access_end -1: // w_access (test failed) +1: // w_access (write succeeded, violating read-only) li x30, 0xBAD 2: // r_access end sd x30, 0(x6) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S index 2367a32bb..695c75222 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S @@ -25,7 +25,7 @@ INIT_TESTS -// Test 5.2.3.1: tersting Read-only access to Machine info CSRs +// Test 5.2.3.1: testing Read-only access to Machine info CSRs csr_r_access mvendorid csr_r_access marchid