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Merge branch 'main' into cache

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This commit is contained in:
Jarred Allen 2021-03-22 14:50:22 -04:00
commit 507d8ed120
2 changed files with 10 additions and 4 deletions
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2
wally-pipelined/regression/regression-wally.py
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@ -27,7 +27,7 @@ def test_config(config, print_res=True):
cmd = "echo 'quit' | vsim -do wally-busybear.do -c >" + logname cmd = "echo 'quit' | vsim -do wally-busybear.do -c >" + logname
os.system(cmd) os.system(cmd)
# check for success. grep returns 0 if found, 1 if not found # check for success. grep returns 0 if found, 1 if not found
passed = search_log_for_text("# loaded 100000 instructions", logname) passed = search_log_for_text("# loaded 200000 instructions", logname)
else: else:
cmd = "vsim -c >" + logname +" <<!\ndo wally-pipelined-batch.do ../config/" + config + " " + config + "\n!\n" cmd = "vsim -c >" + logname +" <<!\ndo wally-pipelined-batch.do ../config/" + config + " " + config + "\n!\n"
print(cmd) print(cmd)

12
wally-pipelined/testbench/testbench-busybear.sv
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@ -190,15 +190,17 @@ module testbench_busybear();
logic [`XLEN-1:0] readAdrExpected; logic [`XLEN-1:0] readAdrExpected;
always @(dut.hart.MemRWM[1] or HADDR or dut.HRDATA) begin //always @(dut.hart.MemRWM[1] or HADDR or dut.HRDATA) begin
if (dut.hart.MemRWM[1] && HADDR != dut.PCF && dut.HRDATA != {64{1'bx}}) begin always @(posedge dut.HREADY) begin
#1;
if (dut.hart.MemRWM[1] && HADDR != dut.PCF && dut.HRDATA !== {64{1'bx}}) begin
$display("%0t", $time);
if($feof(data_file_memR)) begin if($feof(data_file_memR)) begin
$display("no more memR data to read"); $display("no more memR data to read");
`ERROR `ERROR
end end
scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected); scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA); scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA);
#2;
if (~equal(HADDR,readAdrExpected,4)) begin if (~equal(HADDR,readAdrExpected,4)) begin
$display("%0t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected); $display("%0t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected);
`ERROR `ERROR
@ -209,7 +211,11 @@ module testbench_busybear();
warningCount += 1; warningCount += 1;
`ERROR `ERROR
end end
end else if(dut.hart.MemRWM[1]) begin
$display("%x, %x, %x, %t", HADDR, dut.PCF, dut.HRDATA, $time);
end end
end end
logic [`XLEN-1:0] writeDataExpected, writeAdrExpected; logic [`XLEN-1:0] writeDataExpected, writeAdrExpected;