diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py
index 68957cae4..941a7e757 100755
--- a/wally-pipelined/regression/regression-wally.py
+++ b/wally-pipelined/regression/regression-wally.py
@@ -27,7 +27,7 @@ def test_config(config, print_res=True):
     cmd = "echo 'quit' | vsim -do wally-busybear.do -c >" + logname
     os.system(cmd)
     # check for success.  grep returns 0 if found, 1 if not found
-    passed = search_log_for_text("# loaded 100000 instructions", logname)
+    passed = search_log_for_text("# loaded 200000 instructions", logname)
   else:
     cmd = "vsim -c >" + logname +" <<!\ndo wally-pipelined-batch.do ../config/" + config + " " + config + "\n!\n"
     print(cmd)
diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv
index df1e6e49f..a4e2667d3 100644
--- a/wally-pipelined/testbench/testbench-busybear.sv
+++ b/wally-pipelined/testbench/testbench-busybear.sv
@@ -190,15 +190,17 @@ module testbench_busybear();
 
   logic [`XLEN-1:0] readAdrExpected;
 
-  always @(dut.hart.MemRWM[1] or HADDR or dut.HRDATA) begin
-    if (dut.hart.MemRWM[1] && HADDR != dut.PCF && dut.HRDATA != {64{1'bx}}) begin
+  //always @(dut.hart.MemRWM[1] or HADDR or dut.HRDATA) begin
+  always @(posedge dut.HREADY) begin
+    #1;
+    if (dut.hart.MemRWM[1] && HADDR != dut.PCF && dut.HRDATA !== {64{1'bx}}) begin
+      $display("%0t", $time);
       if($feof(data_file_memR)) begin
         $display("no more memR data to read");
         `ERROR
       end
       scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
       scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA);
-      #2;
       if (~equal(HADDR,readAdrExpected,4)) begin
         $display("%0t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected);
         `ERROR
@@ -209,7 +211,11 @@ module testbench_busybear();
         warningCount += 1;
         `ERROR
       end
+    end else if(dut.hart.MemRWM[1]) begin
+      $display("%x, %x, %x, %t", HADDR, dut.PCF, dut.HRDATA, $time);
+
     end
+
   end
 
   logic [`XLEN-1:0] writeDataExpected, writeAdrExpected;