Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

pipelined/src/cache/cache.sv

@@ -56,9 +56,9 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   output logic                  CacheFetchLine,
   output logic                  CacheWriteLine,
   input logic                   CacheBusAck,
-  input logic                   SelLSUBusWord, 
+  input logic                   SelBusWord, 
   input logic [LOGBWPL-1:0]     WordCount,
-  input logic [LINELEN-1:0]     LSUBusBuffer,
+  input logic [LINELEN-1:0]     FetchBuffer,
   output logic [`PA_BITS-1:0]   CacheBusAdr,
   output logic [WORDLEN-1:0]    ReadDataWord);
 
@@ -146,11 +146,11 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   // like to fix this.
   if(DCACHE) 
     mux2 #(LOGBWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]), 
-      .d1(WordCount), .s(SelLSUBusWord),
+      .d1(WordCount), .s(SelBusWord),
       .y(WordOffsetAddr)); 
   else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)];
   
-  mux2 #(LINELEN) EarlyReturnMux(ReadDataLineCache, LSUBusBuffer, SelBusBuffer, ReadDataLine);
+  mux2 #(LINELEN) EarlyReturnMux(ReadDataLineCache, FetchBuffer, SelBusBuffer, ReadDataLine);
 
   subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL) subcachelineread(
     .PAdr(WordOffsetAddr),
@@ -173,10 +173,9 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
 
   for(index = 0; index < LINELEN/8; index++) begin
     mux2 #(8) WriteDataMux(.d0(FinalWriteDataDup[8*index+7:8*index]),
-      .d1(LSUBusBuffer[8*index+7:8*index]), .s(LineByteMux[index]), .y(CacheWriteData[8*index+7:8*index]));
+      .d1(FetchBuffer[8*index+7:8*index]), .s(LineByteMux[index]), .y(CacheWriteData[8*index+7:8*index]));
   end
-  //mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}),
+
-//  .d1(LSUBusBuffer),	.s(SetValid), .y(CacheWriteData));
   mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
 		.d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
 		.d2({VictimTag, FlushAdr, {OFFSETLEN{1'b0}}}),

pipelined/src/ebu/ahblite.sv

@@ -41,29 +41,27 @@ module ahblite (
   input logic 				 UnsignedLoadM,
   input logic [1:0] 		 AtomicMaskedM,
   // Signals from Instruction Cache
-  input logic [`PA_BITS-1:0] IFUBusAdr, 
+  input logic [`PA_BITS-1:0] IFUHADDR, 
+  input logic [2:0]    IFUHBURST,
+  input logic [1:0]    IFUHTRANS,
   input logic 				 IFUBusRead,
-  output logic [`XLEN-1:0] 	 IFUBusHRDATA,
-  output logic 				 IFUBusAck,
-  output logic         IFUBusInit,
-  input logic [2:0]    IFUBurstType,
-  input logic [1:0]    IFUTransType,
   input logic          IFUTransComplete,
+  output logic         IFUBusInit,
+  output logic 				 IFUBusAck,
 
   // Signals from Data Cache
-  input logic [`PA_BITS-1:0] LSUBusAdr,
+  input logic [`PA_BITS-1:0] LSUHADDR,
+  input logic [`XLEN-1:0] 	 LSUHWDATA,
+  input logic [2:0] 		 LSUHSIZE,
+  input logic [2:0]      LSUHBURST,
+  input logic [1:0]    LSUHTRANS,
   input logic 				 LSUBusRead, 
   input logic 				 LSUBusWrite,
-  input logic [`XLEN-1:0] 	 LSUBusHWDATA,
-  output logic [`XLEN-1:0] 	 LSUBusHRDATA,
-  input logic [2:0] 		 LSUBusSize,
-  input logic [2:0]      LSUBurstType,
-  input logic [1:0]    LSUTransType,
   input logic          LSUTransComplete,
-  output logic 				 LSUBusAck,
   output logic         LSUBusInit,
+  output logic 				 LSUBusAck,
+
   // AHB-Lite external signals
-  (* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA,
   (* mark_debug = "true" *) input logic HREADY, HRESP,
   (* mark_debug = "true" *) output logic HCLK, HRESETn,
   (* mark_debug = "true" *) output logic [31:0] HADDR, // *** one day switch to a different bus that supports the full physical address
@@ -85,9 +83,7 @@ module ahblite (
   statetype BusState, NextBusState;
 
   logic LSUGrant;
-  logic [31:0] AccessAddress;
+ 
-  logic [2:0] ISize;
-
   assign HCLK = clk;
   assign HRESETn = ~reset;
 
@@ -131,13 +127,11 @@ module ahblite (
     endcase
 
 
-  //  bus outputs
+  //  LSU/IFU mux: choose source of access
   assign #1 LSUGrant = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
-  assign AccessAddress = (LSUGrant) ? LSUBusAdr[31:0] : IFUBusAdr[31:0];
+  assign HADDR = LSUGrant ? LSUHADDR[31:0] : IFUHADDR[31:0];
-  assign HADDR = AccessAddress;
+  assign HSIZE = LSUGrant ? {1'b0, LSUHSIZE[1:0]} : 3'b010; // Instruction reads are always 32 bits
-  assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
+  assign HBURST = LSUGrant ? LSUHBURST : IFUHBURST; // If doing memory accesses, use LSUburst, else use Instruction burst.
-  assign HSIZE = (LSUGrant) ? {1'b0, LSUBusSize[1:0]} : ISize;
-  assign HBURST = (LSUGrant) ? LSUBurstType : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst.
 
   /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE.
         000: Single (SINGLE)
@@ -153,23 +147,20 @@ module ahblite (
 
 
   assign HPROT = 4'b0011; // not used; see Section 3.7
-  assign HTRANS = (LSUGrant) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
+  assign HTRANS = LSUGrant ? LSUHTRANS : IFUHTRANS; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
   assign HMASTLOCK = 0; // no locking supported
   assign HWRITE = (NextBusState == MEMWRITE);
   // Byte mask for HWSTRB
   swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(HWSTRB));
 
   // delay write data by one cycle for
-  flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
+  flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
   // delay signals for subword writes
   flop #(3)   adrreg(HCLK, HADDR[2:0], HADDRD);
   flop #(4)   sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
   flop #(1)   writereg(HCLK, HWRITE, HWRITED);
 
-    // Route signals to Instruction and Data Caches
+  // Send control back to IFU and LSU
-  // *** assumes AHBW = XLEN
-  assign IFUBusHRDATA = HRDATA;
-  assign LSUBusHRDATA = HRDATA;
   assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD);
   assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState != MEMWRITE) & (NextBusState == MEMWRITE));
   assign IFUBusAck = HREADY & (BusState == INSTRREAD);

pipelined/src/generic/mem/bram2p1r1w.sv

@@ -5,8 +5,8 @@
 // March 29, 2022
 // Modified: Based on UG901 vivado documentation.
 //
-// Purpose: On-chip SIMPLERAM, external to core
+/// Purpose: On-chip RAM array
-// 
+//
 // A component of the Wally configurable RISC-V project.
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University

pipelined/src/ifu/ifu.sv

@@ -36,14 +36,14 @@ module ifu (
 	input logic 				StallF, StallD, StallE, StallM, 
 	input logic 				FlushF, FlushD, FlushE, FlushM, 
 	// Bus interface
-(* mark_debug = "true" *)	input logic [`XLEN-1:0] 	IFUBusHRDATA,
+(* mark_debug = "true" *)	input logic [`XLEN-1:0] 	HRDATA,
 (* mark_debug = "true" *)	input logic 				IFUBusAck,
 (* mark_debug = "true" *)	input logic 				IFUBusInit,
-(* mark_debug = "true" *)	output logic [`PA_BITS-1:0] IFUBusAdr,
+(* mark_debug = "true" *)	output logic [`PA_BITS-1:0] IFUHADDR,
 (* mark_debug = "true" *)	output logic 				IFUBusRead,
 (* mark_debug = "true" *)	output logic 				IFUStallF,
-(* mark_debug = "true" *) output logic [2:0]  IFUBurstType,
+(* mark_debug = "true" *) output logic [2:0]  IFUHBURST,
-(* mark_debug = "true" *) output logic [1:0]  IFUTransType,
+(* mark_debug = "true" *) output logic [1:0]  IFUHTRANS,
 (* mark_debug = "true" *) output logic        IFUTransComplete,
 	(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, 
 	// Execute
@@ -184,10 +184,8 @@ module ifu (
   logic [`XLEN-1:0] AllInstrRawF;
   assign InstrRawF = AllInstrRawF[31:0];
 
-  if (`IROM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name.  Probably use a ROM rather than DTIM
+  if (`IROM) begin : irom 
-    irom irom(.clk, .reset, .LSURWM(2'b10), .IEUAdrE(PCNextFSpill),
+    irom irom(.clk, .reset, .Adr(PCNextFSpill), .ReadData(FinalInstrRawF));
-              .TrapM(1'b0), 
-              .ReadDataWordM({{(`XLEN-32){1'b0}}, FinalInstrRawF}));
  
     assign {BusStall, IFUBusRead} = '0;   
     assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
@@ -196,25 +194,26 @@ module ifu (
     localparam integer   WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
     localparam integer   LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
     localparam integer   LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;
-    logic [LINELEN-1:0]  ILSUBusBuffer;
+    logic [LINELEN-1:0]  FetchBuffer;
     logic [`PA_BITS-1:0] ICacheBusAdr;
     logic                ICacheBusAck;
     logic                SelUncachedAdr;
     
     busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) 
     busdp(.clk, .reset,
-          .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusInit(IFUBusInit), .LSUBusWrite(), .SelLSUBusWord(),
+          .HRDATA(HRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelBusWord(),
-          .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUTransComplete(IFUTransComplete),
+          .BusRead(IFUBusRead), .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .BusTransComplete(IFUTransComplete),
-          .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr),
+          .Funct3(3'b010), .HADDR(IFUHADDR), .CacheBusAdr(ICacheBusAdr),
           .WordCount(), 
-          .DCacheFetchLine(ICacheFetchLine),
+          .CacheFetchLine(ICacheFetchLine),
-          .DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck), 
+          .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck), 
-          .DLSUBusBuffer(ILSUBusBuffer), .LSUPAdrM(PCPF),
+          .FetchBuffer, .PAdr(PCPF),
           .SelUncachedAdr,
-          .IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF),
+          .IgnoreRequest(ITLBMissF), .RW(2'b10), .CPUBusy, .Cacheable(CacheableF),
-          .BusStall, .BusCommittedM());
+          .BusStall, .BusCommitted());
 
-    mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(ILSUBusBuffer[32-1:0]),
+    
+    mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]),
       .s(SelUncachedAdr), .y(AllInstrRawF[31:0]));
     
 
@@ -223,13 +222,13 @@ module ifu (
               .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
               .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
       icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM,
-             .LSUBusBuffer(ILSUBusBuffer), .CacheBusAck(ICacheBusAck),
+             .FetchBuffer, .CacheBusAck(ICacheBusAck),
              .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), 
              .CacheFetchLine(ICacheFetchLine),
              .CacheWriteLine(), .ReadDataWord(FinalInstrRawF),
              .Cacheable(CacheableF),
              .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
-             .ByteMask('0), .WordCount('0), .SelLSUBusWord('0),
+             .ByteMask('0), .WordCount('0), .SelBusWord('0),
              .FinalWriteData('0),
              .RW(2'b10), 
              .Atomic('0), .FlushCache('0),

pipelined/src/ifu/irom.sv

@@ -0,0 +1,46 @@
+///////////////////////////////////////////
+// irom.sv
+//
+// Written: Ross Thompson ross1728@gmail.com January 30, 2022
+// Modified: 
+//
+// Purpose: simple instruction ROM
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// MIT LICENSE
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
+// software and associated documentation files (the "Software"), to deal in the Software 
+// without restriction, including without limitation the rights to use, copy, modify, merge, 
+// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
+// to whom the Software is furnished to do so, subject to the following conditions:
+//
+//   The above copyright notice and this permission notice shall be included in all copies or 
+//   substantial portions of the Software.
+//
+//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+//   OR OTHER DEALINGS IN THE SOFTWARE.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module irom(
+  input logic               clk, reset,
+  input logic [`XLEN-1:0]   Adr,
+  output logic [31:0]  ReadData
+);
+
+ 
+//  localparam ADDR_WDITH = $clog2(`IROM_RAM_RANGE/8);  // *** replace with tihs when  defined
+  localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size
+  localparam OFFSET = $clog2(`LLEN/8);
+
+  brom1p1rw #(ADDR_WDITH, 32) 
+    rom(.clk, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadData));
+endmodule  
+  

pipelined/src/lsu/busdp.sv

@@ -37,59 +37,59 @@
 module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
   (
   input logic                 clk, reset,
+  
   // bus interface
-  input logic [`XLEN-1:0]     LSUBusHRDATA,
+  input logic [`XLEN-1:0]     HRDATA,
-  input logic                 LSUBusAck,
+  input logic                 BusAck,
-  input logic                 LSUBusInit,
+  input logic                 BusInit,
-  output logic                LSUBusWrite,
+  output logic                BusWrite,
-  output logic                LSUBusRead,
+  output logic                BusRead,
-  output logic [2:0]          LSUBusSize,
+  output logic [2:0]          HSIZE,
-  output logic [2:0]          LSUBurstType,
+  output logic [2:0]          HBURST,
-  output logic [1:0]          LSUTransType, // For AHBLite
+  output logic [1:0]          HTRANS,
-  output logic                LSUTransComplete,
+  output logic                BusTransComplete,
-  input logic [2:0]           LSUFunct3M,
+  output logic [`PA_BITS-1:0] HADDR,
-  output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite.
   output logic [LOGWPL-1:0]   WordCount,
-  // cache interface.
+  
-  input logic [`PA_BITS-1:0]  DCacheBusAdr,
+  // cache interface
-  input logic                 DCacheFetchLine,
+  input logic [`PA_BITS-1:0]  CacheBusAdr,
-  input logic                 DCacheWriteLine,
+  input logic                 CacheFetchLine,
-  output logic                DCacheBusAck,
+  input logic                 CacheWriteLine,
-  output logic [LINELEN-1:0]  DLSUBusBuffer, //*** change name.
+  output logic                CacheBusAck,
+  output logic [LINELEN-1:0]  FetchBuffer, 
   output logic                SelUncachedAdr,
  
-  // lsu interface
+  // lsu/ifu interface
-  input logic [`PA_BITS-1:0]  LSUPAdrM,
+  input logic [`PA_BITS-1:0]  PAdr,
   input logic                 IgnoreRequest,
-  input logic [1:0]           LSURWM,
+  input logic [1:0]           RW,
   input logic                 CPUBusy,
-  input logic                 CacheableM,
+  input logic                 Cacheable,
-  output logic                SelLSUBusWord,
+  input logic [2:0]           Funct3,
+  output logic                SelBusWord,
   output logic                BusStall,
-  output logic                BusCommittedM);
+  output logic                BusCommitted);
   
   localparam integer   WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0;
-  logic [`PA_BITS-1:0]        LocalLSUBusAdr;
+  logic [`PA_BITS-1:0]        LocalHADDR;
   logic [LOGWPL-1:0]   WordCountDelayed;
   logic                BufferCaptureEn;
 
-  // *** implement flops as an array if feasbile; DLSUBusBuffer might be a problem
-  // *** better name than DLSUBusBuffer
   genvar                      index;
   for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
     logic [WORDSPERLINE-1:0] CaptureWord;
     assign CaptureWord[index] = BufferCaptureEn & (index == WordCountDelayed);
-    flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(LSUBusHRDATA),
+    flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(HRDATA),
-      .q(DLSUBusBuffer[(index+1)*`XLEN-1:index*`XLEN]));
+      .q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN]));
   end
-  mux2 #(`PA_BITS) localadrmux(DCacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr);
+
-  assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr;
+  mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdr, SelUncachedAdr, LocalHADDR);
-  mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), 
+  assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR;
-    .s(SelUncachedAdr), .y(LSUBusSize));
+
+  mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE));
 
   busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm(
-    .clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine,
+    .clk, .reset, .IgnoreRequest, .RW, .CacheFetchLine, .CacheWriteLine,
-		.LSUBusAck, .LSUBusInit, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .SelLSUBusWord, .LSUBusRead,
+		.BusAck, .BusInit, .CPUBusy, .Cacheable, .BusStall, .BusWrite, .SelBusWord, .BusRead, .BufferCaptureEn,
-        .BufferCaptureEn,
+		.HBURST, .HTRANS, .BusTransComplete, .CacheBusAck, .BusCommitted, .SelUncachedAdr, .WordCount, .WordCountDelayed);
-		.LSUBurstType, .LSUTransType, .LSUTransComplete, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed);
 endmodule

pipelined/src/lsu/busfsm.sv

@@ -37,31 +37,31 @@ module busfsm #(parameter integer   WordCountThreshold,
    input logic               reset,
 
    input logic               IgnoreRequest,
-   input logic [1:0]         LSURWM,
+   input logic [1:0]         RW,
-   input logic               DCacheFetchLine,
+   input logic               CacheFetchLine,
-   input logic               DCacheWriteLine,
+   input logic               CacheWriteLine,
-   input logic               LSUBusAck,
+   input logic               BusAck,
-   input logic               LSUBusInit, // This might be better as LSUBusLock, or to send this using LSUBusAck.
+   input logic               BusInit, // This might be better as LSUBusLock, or to send this using BusAck.
    input logic               CPUBusy,
-   input logic               CacheableM,
+   input logic               Cacheable,
 
    output logic              BusStall,
-   output logic              LSUBusWrite,
+   output logic              BusWrite,
-   output logic              SelLSUBusWord,
+   output logic              SelBusWord,
-   output logic              LSUBusRead,
+   output logic              BusRead,
-   output logic [2:0]        LSUBurstType,
+   output logic [2:0]        HBURST,
-   output logic              LSUTransComplete,
+   output logic              BusTransComplete,
-   output logic [1:0]        LSUTransType,
+   output logic [1:0]        HTRANS,
-   output logic              DCacheBusAck,
+   output logic              CacheBusAck,
-   output logic              BusCommittedM,
+   output logic              BusCommitted,
    output logic              SelUncachedAdr,
    output logic              BufferCaptureEn,
    output logic [LOGWPL-1:0] WordCount, WordCountDelayed);
   
 
   
-  logic 			   UnCachedLSUBusRead;
+  logic 			   UnCachedBusRead;
-  logic 			   UnCachedLSUBusWrite;
+  logic 			   UnCachedBusWrite;
   logic 			   CntEn, PreCntEn;
   logic 			   CntReset;
   logic 			   WordCountFlag;
@@ -103,9 +103,9 @@ module busfsm #(parameter integer   WordCountThreshold,
 
   assign PreCntEn = (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE);
   assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); // Detect when we are waiting on the final access.
-  assign CntEn = (PreCntEn & LSUBusAck | (LSUBusInit)) & ~WordCountFlag & ~UnCachedRW; // Want to count when doing cache accesses and we aren't wrapping up.
+  assign CntEn = (PreCntEn & BusAck | (BusInit)) & ~WordCountFlag & ~UnCachedRW; // Want to count when doing cache accesses and we aren't wrapping up.
 
-  assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM;
+  assign UnCachedAccess = ~CACHE_ENABLED | ~Cacheable;
 
   always_ff @(posedge clk)
     if (reset)    BusCurrState <= #1 STATE_BUS_READY;
@@ -114,14 +114,14 @@ module busfsm #(parameter integer   WordCountThreshold,
   always_comb begin
 	case(BusCurrState)
 	  STATE_BUS_READY:           if(IgnoreRequest)                   BusNextState = STATE_BUS_READY;
-	                             else if(LSURWM[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE;
+	                             else if(RW[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE;
-		                         else if(LSURWM[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ;
+		                         else if(RW[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ;
-		                         else if(DCacheFetchLine)            BusNextState = STATE_BUS_FETCH;
+		                         else if(CacheFetchLine)            BusNextState = STATE_BUS_FETCH;
-		                         else if(DCacheWriteLine)            BusNextState = STATE_BUS_WRITE;
+		                         else if(CacheWriteLine)            BusNextState = STATE_BUS_WRITE;
                                  else                                BusNextState = STATE_BUS_READY;
-      STATE_BUS_UNCACHED_WRITE:  if(LSUBusAck)                       BusNextState = STATE_BUS_UNCACHED_WRITE_DONE;
+      STATE_BUS_UNCACHED_WRITE:  if(BusAck)                       BusNextState = STATE_BUS_UNCACHED_WRITE_DONE;
 		                         else                                BusNextState = STATE_BUS_UNCACHED_WRITE;
-      STATE_BUS_UNCACHED_READ:   if(LSUBusAck)                       BusNextState = STATE_BUS_UNCACHED_READ_DONE;
+      STATE_BUS_UNCACHED_READ:   if(BusAck)                       BusNextState = STATE_BUS_UNCACHED_READ_DONE;
 		                         else                                BusNextState = STATE_BUS_UNCACHED_READ;
       STATE_BUS_UNCACHED_WRITE_DONE: if(CPUBusy)                     BusNextState = STATE_BUS_CPU_BUSY;
                                      else                            BusNextState = STATE_BUS_READY;
@@ -129,14 +129,14 @@ module busfsm #(parameter integer   WordCountThreshold,
                                      else                            BusNextState = STATE_BUS_READY;
 	  STATE_BUS_CPU_BUSY:            if(CPUBusy)                     BusNextState = STATE_BUS_CPU_BUSY;
                                      else                            BusNextState = STATE_BUS_READY;
-      STATE_BUS_FETCH:           if (WordCountFlag & LSUBusAck) begin
+      STATE_BUS_FETCH:           if (WordCountFlag & BusAck) begin
-                                   if (DCacheFetchLine)  BusNextState = STATE_BUS_FETCH;
+                                   if (CacheFetchLine)  BusNextState = STATE_BUS_FETCH;
-                                   else if (DCacheWriteLine)  BusNextState = STATE_BUS_WRITE;
+                                   else if (CacheWriteLine)  BusNextState = STATE_BUS_WRITE;
                                    else BusNextState = STATE_BUS_READY;
 	                             end else                            BusNextState = STATE_BUS_FETCH;
-      STATE_BUS_WRITE:           if(WordCountFlag & LSUBusAck) begin
+      STATE_BUS_WRITE:           if(WordCountFlag & BusAck) begin
-                                   if (DCacheFetchLine)  BusNextState = STATE_BUS_FETCH;
+                                   if (CacheFetchLine)  BusNextState = STATE_BUS_FETCH;
-                                   else if (DCacheWriteLine)  BusNextState = STATE_BUS_WRITE;
+                                   else if (CacheWriteLine)  BusNextState = STATE_BUS_WRITE;
                                    else  BusNextState = STATE_BUS_READY;
                                  end else                                BusNextState = STATE_BUS_WRITE;
 	  default:                                                       BusNextState = STATE_BUS_READY;
@@ -153,41 +153,40 @@ module busfsm #(parameter integer   WordCountThreshold,
     endcase
   end
 
-  // Would these be better as always_comb statements or muxes?
+   assign HBURST = (UnCachedRW) ? 3'b0 : LocalBurstType; // Don't want to use burst when doing an Uncached Access.
-  assign LSUBurstType = (UnCachedRW) ? 3'b0 : LocalBurstType; // Don't want to use burst when doing an Uncached Access.
+  assign BusTransComplete = (UnCachedRW) ? BusAck : WordCountFlag & BusAck;
-  assign LSUTransComplete = (UnCachedRW) ? LSUBusAck : WordCountFlag & LSUBusAck;
   // Use SEQ if not doing first word, NONSEQ if doing the first read/write, and IDLE if finishing up.
-  assign LSUTransType = (|WordCount) & ~UnCachedRW ? AHB_SEQ : (LSUBusRead | LSUBusWrite) & (~LSUTransComplete) ? AHB_NONSEQ : AHB_IDLE; 
+  assign HTRANS = (|WordCount) & ~UnCachedRW ? AHB_SEQ : (BusRead | BusWrite) & (~BusTransComplete) ? AHB_NONSEQ : AHB_IDLE; 
   // Reset if we aren't initiating a transaction or if we are finishing a transaction.
-  assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine) | LSUTransComplete; 
+  assign CntReset = BusCurrState == STATE_BUS_READY & ~(CacheFetchLine | CacheWriteLine) | BusTransComplete; 
   
-  assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) |
+  assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|RW)) | CacheFetchLine | CacheWriteLine)) |
 					(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
 					(BusCurrState == STATE_BUS_UNCACHED_READ) |
 					(BusCurrState == STATE_BUS_FETCH)  |
 					(BusCurrState == STATE_BUS_WRITE);
-  assign UnCachedLSUBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) |
+  assign UnCachedBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RW[0] & ~IgnoreRequest) |
 							   (BusCurrState == STATE_BUS_UNCACHED_WRITE);
-  assign LSUBusWrite = UnCachedLSUBusWrite | (BusCurrState == STATE_BUS_WRITE & ~WordCountFlag);
+  assign BusWrite = UnCachedBusWrite | (BusCurrState == STATE_BUS_WRITE & ~WordCountFlag);
-  assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0]) |
+  assign SelBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RW[0]) |
 						   (BusCurrState == STATE_BUS_UNCACHED_WRITE) |
                            (BusCurrState == STATE_BUS_WRITE);
 
-  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
+  assign UnCachedBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RW[1] & ~IgnoreRequest) |
 							  (BusCurrState == STATE_BUS_UNCACHED_READ);
-  assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine);
+  assign BusRead = UnCachedBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & CacheFetchLine);
-  assign BufferCaptureEn = UnCachedLSUBusRead | BusCurrState == STATE_BUS_FETCH;
+  assign BufferCaptureEn = UnCachedBusRead | BusCurrState == STATE_BUS_FETCH;
 
-  // Makes bus only do uncached reads/writes when we actually do uncached reads/writes. Needed because CacheableM is 0 when flushing cache.
+  // Makes bus only do uncached reads/writes when we actually do uncached reads/writes. Needed because Cacheable is 0 when flushing cache.
-  assign UnCachedRW = UnCachedLSUBusWrite | UnCachedLSUBusRead; 
+  assign UnCachedRW = UnCachedBusWrite | UnCachedBusRead; 
 
-  assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LSUBusAck) |
+  assign CacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & BusAck) |
-						(BusCurrState == STATE_BUS_WRITE & WordCountFlag & LSUBusAck);
+						(BusCurrState == STATE_BUS_WRITE & WordCountFlag & BusAck);
-  assign BusCommittedM = BusCurrState != STATE_BUS_READY;
+  assign BusCommitted = BusCurrState != STATE_BUS_READY;
-  assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LSURWM & UnCachedAccess)) |
+  assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|RW & UnCachedAccess)) |
 						  (BusCurrState == STATE_BUS_UNCACHED_READ |
 						   BusCurrState == STATE_BUS_UNCACHED_READ_DONE |
 						   BusCurrState == STATE_BUS_UNCACHED_WRITE |
 						   BusCurrState == STATE_BUS_UNCACHED_WRITE_DONE) |
-						  ~CACHE_ENABLED; // if no dcache always select uncachedadr.
+						  ~CACHE_ENABLED; // if no Cache always select uncachedadr.
 endmodule

pipelined/src/lsu/lsu.sv

@@ -65,16 +65,16 @@ module lsu (
    // cpu hazard unit (trap)
    output logic             StoreAmoMisalignedFaultM, StoreAmoAccessFaultM,
             // connect to ahb
-   (* mark_debug = "true" *)   output logic [`PA_BITS-1:0] LSUBusAdr,
+   (* mark_debug = "true" *)   output logic [`PA_BITS-1:0] LSUHADDR,
    (* mark_debug = "true" *)   output logic LSUBusRead, 
    (* mark_debug = "true" *)   output logic LSUBusWrite,
    (* mark_debug = "true" *)   input logic LSUBusAck,
    (* mark_debug = "true" *)   input logic LSUBusInit,
-   (* mark_debug = "true" *)   input logic [`XLEN-1:0] LSUBusHRDATA,
+   (* mark_debug = "true" *)   input logic [`XLEN-1:0] HRDATA,
-   (* mark_debug = "true" *)   output logic [`XLEN-1:0] LSUBusHWDATA,
+   (* mark_debug = "true" *)   output logic [`XLEN-1:0] LSUHWDATA,
-   (* mark_debug = "true" *)   output logic [2:0] LSUBusSize, 
+   (* mark_debug = "true" *)   output logic [2:0] LSUHSIZE, 
-   (* mark_debug = "true" *)   output logic [2:0] LSUBurstType,
+   (* mark_debug = "true" *)   output logic [2:0] LSUHBURST,
-   (* mark_debug = "true" *)   output logic [1:0] LSUTransType,
+   (* mark_debug = "true" *)   output logic [1:0] LSUHTRANS,
    (* mark_debug = "true" *)   output logic LSUTransComplete,
             // page table walker
    input logic [`XLEN-1:0]  SATP_REGW, // from csr
@@ -108,7 +108,7 @@ module lsu (
   logic                     InterlockStall;
   logic                     IgnoreRequestTLB;
   logic                     BusCommittedM, DCacheCommittedM;
-  logic                     SelLSUBusWord;
+  logic                     SelBusWord;
   logic                     DataDAPageFaultM;
   logic [`XLEN-1:0]         IMWriteDataM, IMAWriteDataM;
   logic [`LLEN-1:0]         IMAFWriteDataM;
@@ -198,9 +198,10 @@ module lsu (
   
   // The LSU allows both a DTIM and bus with cache.  However, the PMA decoding presently 
   // use the same UNCORE_RAM_BASE addresss for both the DTIM and any RAM in the Uncore.
+  // *** becomes DTIM_RAM_BASE
 
   if (`DMEM) begin : dtim
-    dtim dtim(.clk, .reset, .LSURWM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM), //*** fix the dtim FinalWriteData - is this done already?
+    dtim dtim(.clk, .reset, .LSURWM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM), 
               .ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]), .Cacheable(CacheableM));
 
     // since we have a local memory the bus connections are all disabled.
@@ -214,7 +215,7 @@ module lsu (
     localparam integer   WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1;
     localparam integer   LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN;
     localparam integer   LOGBWPL = `DCACHE ? $clog2(WORDSPERLINE) : 1;
-    logic [LINELEN-1:0]  DLSUBusBuffer;
+    logic [LINELEN-1:0]  FetchBuffer;
     logic [`PA_BITS-1:0] DCacheBusAdr;
     logic                DCacheWriteLine;
     logic                DCacheFetchLine;
@@ -223,28 +224,29 @@ module lsu (
             
     busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) busdp(
       .clk, .reset,
-      .LSUBusHRDATA, .LSUBusAck, .LSUBusInit, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete,
+      .HRDATA, .BusAck(LSUBusAck), .BusInit(LSUBusInit), .BusWrite(LSUBusWrite), 
-      .WordCount, .SelLSUBusWord,
+      .BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete),
-      .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine,
+      .WordCount, .SelBusWord,
-      .DCacheWriteLine, .DCacheBusAck, .DLSUBusBuffer, .LSUPAdrM,
+      .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine),
-      .SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM,
+      .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM),
-      .BusStall, .BusCommittedM);
+      .SelUncachedAdr, .IgnoreRequest, .RW(LSURWM), .CPUBusy, .Cacheable(CacheableM),
+      .BusStall, .BusCommitted(BusCommittedM));
 
-    mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, DLSUBusBuffer[`XLEN-1:0]}),
+    mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}),
       .s(SelUncachedAdr), .y(ReadDataWordMuxM));
-    mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]),
+    mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]),
-      .s(SelUncachedAdr), .y(LSUBusHWDATA));
+      .s(SelUncachedAdr), .y(LSUHWDATA));
     if(`DCACHE) begin : dcache
       cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
               .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
-        .clk, .reset, .CPUBusy, .SelLSUBusWord, .RW(LSURWM), .Atomic(LSUAtomicM),
+        .clk, .reset, .CPUBusy, .SelBusWord, .RW(LSURWM), .Atomic(LSUAtomicM),
         .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), 
         .ByteMask(ByteMaskM), .WordCount,
         .FinalWriteData(LSUWriteDataM), .Cacheable(CacheableM),
         .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
         .IgnoreRequestTLB, .TrapM, .CacheCommitted(DCacheCommittedM), 
         .CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM), 
-        .LSUBusBuffer(DLSUBusBuffer), .CacheFetchLine(DCacheFetchLine), 
+        .FetchBuffer, .CacheFetchLine(DCacheFetchLine), 
         .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
 
     end else begin : passthrough
@@ -252,7 +254,7 @@ module lsu (
       assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM;
     end
   end else begin: nobus // block: bus
-    assign {LSUBusHWDATA, SelUncachedAdr} = '0; 
+    assign {LSUHWDATA, SelUncachedAdr} = '0; 
     assign ReadDataWordMuxM = LittleEndianReadDataWordM;
   end
 

pipelined/src/wally/wallypipelinedcore.sv

@@ -136,21 +136,19 @@ module wallypipelinedcore (
   logic             CommittedM;
 
   // AHB ifu interface
-  logic [`PA_BITS-1:0]         IFUBusAdr;
+  logic [`PA_BITS-1:0]         IFUHADDR;
-  logic [`XLEN-1:0]         IFUBusHRDATA;
   logic             IFUBusRead;
   logic             IFUBusAck, IFUBusInit;
-  logic [2:0]       IFUBurstType;
+  logic [2:0]       IFUHBURST;
-  logic [1:0]       IFUTransType;
+  logic [1:0]       IFUHTRANS;
   logic             IFUTransComplete;
   
   // AHB LSU interface
-  logic [`PA_BITS-1:0]         LSUBusAdr;
+  logic [`PA_BITS-1:0]         LSUHADDR;
   logic             LSUBusRead;
   logic             LSUBusWrite;
   logic             LSUBusAck, LSUBusInit;
-  logic [`XLEN-1:0]         LSUBusHRDATA;
+  logic [`XLEN-1:0]         LSUHWDATA;
-  logic [`XLEN-1:0]         LSUBusHWDATA;
   
   logic             BPPredWrongE;
   logic             BPPredDirWrongM;
@@ -159,9 +157,9 @@ module wallypipelinedcore (
   logic             BPPredClassNonCFIWrongM;
   logic [4:0]             InstrClassM;
   logic             InstrAccessFaultF;
-  logic [2:0]             LSUBusSize;
+  logic [2:0]             LSUHSIZE;
-  logic [2:0]             LSUBurstType;
+  logic [2:0]             LSUHBURST;
-  logic [1:0]             LSUTransType;
+  logic [1:0]             LSUHTRANS;
   logic             LSUTransComplete;
   
   logic             DCacheMiss;
@@ -178,8 +176,8 @@ module wallypipelinedcore (
     .StallF, .StallD, .StallE, .StallM, 
     .FlushF, .FlushD, .FlushE, .FlushM, 
     // Fetch
-    .IFUBusHRDATA, .IFUBusAck, .IFUBusInit, .PCF, .IFUBusAdr,
+    .HRDATA, .IFUBusAck, .IFUBusInit, .PCF, .IFUHADDR,
-    .IFUBusRead, .IFUStallF, .IFUBurstType, .IFUTransType, .IFUTransComplete,
+    .IFUBusRead, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUTransComplete,
     .ICacheAccess, .ICacheMiss,
 
     // Execute
@@ -263,8 +261,8 @@ module wallypipelinedcore (
   .IEUAdrE, .IEUAdrM, .WriteDataM,
   .ReadDataW, .FlushDCacheM,
   // connected to ahb (all stay the same)
-  .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit,
+  .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit,
-  .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete,
+  .HRDATA, .LSUHWDATA, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete,
 
     // connect to csr or privilege and stay the same.
     .PrivilegeModeW, .BigEndianM,          // connects to csr
@@ -296,24 +294,22 @@ module wallypipelinedcore (
     ahblite ebu(// IFU connections
      .clk, .reset,
      .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),
-     .IFUBusAdr, .IFUBusRead, 
+     .IFUHADDR, .IFUBusRead, 
-     .IFUBusHRDATA, 
+     .IFUHBURST, 
-     .IFUBurstType, 
+     .IFUHTRANS, 
-     .IFUTransType, 
      .IFUTransComplete,
      .IFUBusAck, 
      .IFUBusInit, 
      // Signals from Data Cache
-     .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA,
+     .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUHWDATA,
-     .LSUBusHRDATA,
+     .LSUHSIZE,
-     .LSUBusSize,
+     .LSUHBURST,
-     .LSUBurstType,
+     .LSUHTRANS,
-     .LSUTransType,
      .LSUTransComplete,
      .LSUBusAck,
      .LSUBusInit,
  
-     .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn,
+     .HREADY, .HRESP, .HCLK, .HRESETn,
      .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
      .HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED,
      .HWRITED);