From cb2c0fe027a4c7f2db18ca7c15e1edce50a4d89c Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Aug 2022 04:28:25 -0700 Subject: [PATCH 01/10] Minor name cleanups --- pipelined/src/lsu/busdp.sv | 4 +--- pipelined/src/lsu/busfsm.sv | 3 +-- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index d06ba89b7..e8b182b27 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -73,9 +73,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) logic [LOGWPL-1:0] WordCountDelayed; logic BufferCaptureEn; - // *** implement flops as an array if feasbile; DLSUBusBuffer might be a problem - // *** better name than DLSUBusBuffer - genvar index; + genvar index; for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer logic [WORDSPERLINE-1:0] CaptureWord; assign CaptureWord[index] = BufferCaptureEn & (index == WordCountDelayed); diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index 7b0c63f66..ceae87ab1 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -153,8 +153,7 @@ module busfsm #(parameter integer WordCountThreshold, endcase end - // Would these be better as always_comb statements or muxes? - assign LSUBurstType = (UnCachedRW) ? 3'b0 : LocalBurstType; // Don't want to use burst when doing an Uncached Access. + assign LSUBurstType = (UnCachedRW) ? 3'b0 : LocalBurstType; // Don't want to use burst when doing an Uncached Access. assign LSUTransComplete = (UnCachedRW) ? LSUBusAck : WordCountFlag & LSUBusAck; // Use SEQ if not doing first word, NONSEQ if doing the first read/write, and IDLE if finishing up. assign LSUTransType = (|WordCount) & ~UnCachedRW ? AHB_SEQ : (LSUBusRead | LSUBusWrite) & (~LSUTransComplete) ? AHB_NONSEQ : AHB_IDLE; From b9dc8d9e33e85b76de2154b8671a880ec151ac3e Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Aug 2022 04:32:19 -0700 Subject: [PATCH 02/10] Cleanup typos --- pipelined/src/generic/mem/bram2p1r1w.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/generic/mem/bram2p1r1w.sv b/pipelined/src/generic/mem/bram2p1r1w.sv index de5a09f27..8c66a963a 100644 --- a/pipelined/src/generic/mem/bram2p1r1w.sv +++ b/pipelined/src/generic/mem/bram2p1r1w.sv @@ -5,8 +5,8 @@ // March 29, 2022 // Modified: Based on UG901 vivado documentation. // -// Purpose: On-chip SIMPLERAM, external to core -// +/// Purpose: On-chip RAM array +// // A component of the Wally configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University From 4ecdbb308a497c17fe2eeef8bd205963856cd3d9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Aug 2022 06:21:22 -0700 Subject: [PATCH 03/10] Renamed DCache to Cache in busdp/busfsm signal interface --- pipelined/src/ifu/ifu.sv | 6 +++--- pipelined/src/lsu/busdp.sv | 18 ++++++++++-------- pipelined/src/lsu/busfsm.sv | 28 ++++++++++++++-------------- pipelined/src/lsu/lsu.sv | 4 ++-- 4 files changed, 29 insertions(+), 27 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index c1ac1b8f1..c0bce157b 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -205,10 +205,10 @@ module ifu ( busdp(.clk, .reset, .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusInit(IFUBusInit), .LSUBusWrite(), .SelLSUBusWord(), .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUTransComplete(IFUTransComplete), - .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr), + .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .CacheBusAdr(ICacheBusAdr), .WordCount(), - .DCacheFetchLine(ICacheFetchLine), - .DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck), + .CacheFetchLine(ICacheFetchLine), + .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck), .DLSUBusBuffer(ILSUBusBuffer), .LSUPAdrM(PCPF), .SelUncachedAdr, .IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index e8b182b27..3889b070f 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -37,6 +37,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) ( input logic clk, reset, + // bus interface input logic [`XLEN-1:0] LSUBusHRDATA, input logic LSUBusAck, @@ -50,15 +51,16 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) input logic [2:0] LSUFunct3M, output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite. output logic [LOGWPL-1:0] WordCount, + // cache interface. - input logic [`PA_BITS-1:0] DCacheBusAdr, - input logic DCacheFetchLine, - input logic DCacheWriteLine, - output logic DCacheBusAck, + input logic [`PA_BITS-1:0] CacheBusAdr, + input logic CacheFetchLine, + input logic CacheWriteLine, + output logic CacheBusAck, output logic [LINELEN-1:0] DLSUBusBuffer, //*** change name. output logic SelUncachedAdr, - // lsu interface + // lsu/ifu interface input logic [`PA_BITS-1:0] LSUPAdrM, input logic IgnoreRequest, input logic [1:0] LSURWM, @@ -80,14 +82,14 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(LSUBusHRDATA), .q(DLSUBusBuffer[(index+1)*`XLEN-1:index*`XLEN])); end - mux2 #(`PA_BITS) localadrmux(DCacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr); + mux2 #(`PA_BITS) localadrmux(CacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr); assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr; mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(LSUBusSize)); busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( - .clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, + .clk, .reset, .IgnoreRequest, .LSURWM, .CacheFetchLine, .CacheWriteLine, .LSUBusAck, .LSUBusInit, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .SelLSUBusWord, .LSUBusRead, .BufferCaptureEn, - .LSUBurstType, .LSUTransType, .LSUTransComplete, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); + .LSUBurstType, .LSUTransType, .LSUTransComplete, .CacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index ceae87ab1..f0204f3e4 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -38,8 +38,8 @@ module busfsm #(parameter integer WordCountThreshold, input logic IgnoreRequest, input logic [1:0] LSURWM, - input logic DCacheFetchLine, - input logic DCacheWriteLine, + input logic CacheFetchLine, + input logic CacheWriteLine, input logic LSUBusAck, input logic LSUBusInit, // This might be better as LSUBusLock, or to send this using LSUBusAck. input logic CPUBusy, @@ -52,7 +52,7 @@ module busfsm #(parameter integer WordCountThreshold, output logic [2:0] LSUBurstType, output logic LSUTransComplete, output logic [1:0] LSUTransType, - output logic DCacheBusAck, + output logic CacheBusAck, output logic BusCommittedM, output logic SelUncachedAdr, output logic BufferCaptureEn, @@ -116,8 +116,8 @@ module busfsm #(parameter integer WordCountThreshold, STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; else if(LSURWM[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE; else if(LSURWM[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ; - else if(DCacheFetchLine) BusNextState = STATE_BUS_FETCH; - else if(DCacheWriteLine) BusNextState = STATE_BUS_WRITE; + else if(CacheFetchLine) BusNextState = STATE_BUS_FETCH; + else if(CacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; STATE_BUS_UNCACHED_WRITE: if(LSUBusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; else BusNextState = STATE_BUS_UNCACHED_WRITE; @@ -130,13 +130,13 @@ module busfsm #(parameter integer WordCountThreshold, STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; else BusNextState = STATE_BUS_READY; STATE_BUS_FETCH: if (WordCountFlag & LSUBusAck) begin - if (DCacheFetchLine) BusNextState = STATE_BUS_FETCH; - else if (DCacheWriteLine) BusNextState = STATE_BUS_WRITE; + if (CacheFetchLine) BusNextState = STATE_BUS_FETCH; + else if (CacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; end else BusNextState = STATE_BUS_FETCH; STATE_BUS_WRITE: if(WordCountFlag & LSUBusAck) begin - if (DCacheFetchLine) BusNextState = STATE_BUS_FETCH; - else if (DCacheWriteLine) BusNextState = STATE_BUS_WRITE; + if (CacheFetchLine) BusNextState = STATE_BUS_FETCH; + else if (CacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; end else BusNextState = STATE_BUS_WRITE; default: BusNextState = STATE_BUS_READY; @@ -158,9 +158,9 @@ module busfsm #(parameter integer WordCountThreshold, // Use SEQ if not doing first word, NONSEQ if doing the first read/write, and IDLE if finishing up. assign LSUTransType = (|WordCount) & ~UnCachedRW ? AHB_SEQ : (LSUBusRead | LSUBusWrite) & (~LSUTransComplete) ? AHB_NONSEQ : AHB_IDLE; // Reset if we aren't initiating a transaction or if we are finishing a transaction. - assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine) | LSUTransComplete; + assign CntReset = BusCurrState == STATE_BUS_READY & ~(CacheFetchLine | CacheWriteLine) | LSUTransComplete; - assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | + assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | CacheFetchLine | CacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_FETCH) | @@ -174,13 +174,13 @@ module busfsm #(parameter integer WordCountThreshold, assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_READ); - assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine); + assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & CacheFetchLine); assign BufferCaptureEn = UnCachedLSUBusRead | BusCurrState == STATE_BUS_FETCH; // Makes bus only do uncached reads/writes when we actually do uncached reads/writes. Needed because CacheableM is 0 when flushing cache. assign UnCachedRW = UnCachedLSUBusWrite | UnCachedLSUBusRead; - assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LSUBusAck) | + assign CacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LSUBusAck) | (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LSUBusAck); assign BusCommittedM = BusCurrState != STATE_BUS_READY; assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LSURWM & UnCachedAccess)) | @@ -188,5 +188,5 @@ module busfsm #(parameter integer WordCountThreshold, BusCurrState == STATE_BUS_UNCACHED_READ_DONE | BusCurrState == STATE_BUS_UNCACHED_WRITE | BusCurrState == STATE_BUS_UNCACHED_WRITE_DONE) | - ~CACHE_ENABLED; // if no dcache always select uncachedadr. + ~CACHE_ENABLED; // if no Cache always select uncachedadr. endmodule diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 1b7804d8e..10f8060b6 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -225,8 +225,8 @@ module lsu ( .clk, .reset, .LSUBusHRDATA, .LSUBusAck, .LSUBusInit, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete, .WordCount, .SelLSUBusWord, - .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, - .DCacheWriteLine, .DCacheBusAck, .DLSUBusBuffer, .LSUPAdrM, + .LSUFunct3M, .LSUBusAdr, .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), + .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .DLSUBusBuffer, .LSUPAdrM, .SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .BusStall, .BusCommittedM); From 89860588b8ad33c9c328758700fe49132135b879 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Aug 2022 09:52:08 -0700 Subject: [PATCH 04/10] Renamed AHB signals coming out of LSU to LSH_ --- pipelined/src/ebu/ahblite.sv | 20 ++++----- pipelined/src/ifu/ifu.sv | 7 +-- pipelined/src/lsu/busdp.sv | 40 ++++++++--------- pipelined/src/lsu/busfsm.sv | 52 +++++++++++------------ pipelined/src/lsu/lsu.sv | 18 ++++---- pipelined/src/wally/wallypipelinedcore.sv | 24 +++++------ 6 files changed, 82 insertions(+), 79 deletions(-) diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 0bf81f62a..6c3d0c330 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -51,14 +51,14 @@ module ahblite ( input logic IFUTransComplete, // Signals from Data Cache - input logic [`PA_BITS-1:0] LSUBusAdr, + input logic [`PA_BITS-1:0] LSUHADDR, input logic LSUBusRead, input logic LSUBusWrite, input logic [`XLEN-1:0] LSUBusHWDATA, - output logic [`XLEN-1:0] LSUBusHRDATA, - input logic [2:0] LSUBusSize, - input logic [2:0] LSUBurstType, - input logic [1:0] LSUTransType, + output logic [`XLEN-1:0] LSUHRDATA, + input logic [2:0] LSUHSIZE, + input logic [2:0] LSUHBURST, + input logic [1:0] LSUHTRANS, input logic LSUTransComplete, output logic LSUBusAck, output logic LSUBusInit, @@ -133,11 +133,11 @@ module ahblite ( // bus outputs assign #1 LSUGrant = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); - assign AccessAddress = (LSUGrant) ? LSUBusAdr[31:0] : IFUBusAdr[31:0]; + assign AccessAddress = (LSUGrant) ? LSUHADDR[31:0] : IFUBusAdr[31:0]; assign HADDR = AccessAddress; assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway - assign HSIZE = (LSUGrant) ? {1'b0, LSUBusSize[1:0]} : ISize; - assign HBURST = (LSUGrant) ? LSUBurstType : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst. + assign HSIZE = (LSUGrant) ? {1'b0, LSUHSIZE[1:0]} : ISize; + assign HBURST = (LSUGrant) ? LSUHBURST : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst. /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE. 000: Single (SINGLE) @@ -153,7 +153,7 @@ module ahblite ( assign HPROT = 4'b0011; // not used; see Section 3.7 - assign HTRANS = (LSUGrant) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise + assign HTRANS = (LSUGrant) ? LSUHTRANS : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HMASTLOCK = 0; // no locking supported assign HWRITE = (NextBusState == MEMWRITE); // Byte mask for HWSTRB @@ -169,7 +169,7 @@ module ahblite ( // Route signals to Instruction and Data Caches // *** assumes AHBW = XLEN assign IFUBusHRDATA = HRDATA; - assign LSUBusHRDATA = HRDATA; + assign LSUHRDATA = HRDATA; assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD); assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState != MEMWRITE) & (NextBusState == MEMWRITE)); assign IFUBusAck = HREADY & (BusState == INSTRREAD); diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index c0bce157b..1f3bda8c6 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -203,9 +203,9 @@ module ifu ( busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) busdp(.clk, .reset, - .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusInit(IFUBusInit), .LSUBusWrite(), .SelLSUBusWord(), - .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUTransComplete(IFUTransComplete), - .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .CacheBusAdr(ICacheBusAdr), + .HRDATA(IFUBusHRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelLSUBusWord(), + .BusRead(IFUBusRead), .HSIZE(), .HBURST(IFUBurstType), .HTRANS(IFUTransType), .BusTransComplete(IFUTransComplete), + .LSUFunct3M(3'b010), .HADDR(IFUBusAdr), .CacheBusAdr(ICacheBusAdr), .WordCount(), .CacheFetchLine(ICacheFetchLine), .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck), @@ -214,6 +214,7 @@ module ifu ( .IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF), .BusStall, .BusCommittedM()); + mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(ILSUBusBuffer[32-1:0]), .s(SelUncachedAdr), .y(AllInstrRawF[31:0])); diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 3889b070f..0f0e2b47a 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -39,20 +39,19 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) input logic clk, reset, // bus interface - input logic [`XLEN-1:0] LSUBusHRDATA, - input logic LSUBusAck, - input logic LSUBusInit, - output logic LSUBusWrite, - output logic LSUBusRead, - output logic [2:0] LSUBusSize, - output logic [2:0] LSUBurstType, - output logic [1:0] LSUTransType, // For AHBLite - output logic LSUTransComplete, - input logic [2:0] LSUFunct3M, - output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite. + input logic [`XLEN-1:0] HRDATA, + input logic BusAck, + input logic BusInit, + output logic BusWrite, + output logic BusRead, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [1:0] HTRANS, // For AHBLite + output logic BusTransComplete, + output logic [`PA_BITS-1:0] HADDR, output logic [LOGWPL-1:0] WordCount, - // cache interface. + // cache interface input logic [`PA_BITS-1:0] CacheBusAdr, input logic CacheFetchLine, input logic CacheWriteLine, @@ -66,12 +65,13 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) input logic [1:0] LSURWM, input logic CPUBusy, input logic CacheableM, + input logic [2:0] LSUFunct3M, output logic SelLSUBusWord, output logic BusStall, output logic BusCommittedM); localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; - logic [`PA_BITS-1:0] LocalLSUBusAdr; + logic [`PA_BITS-1:0] LocalHADDR; logic [LOGWPL-1:0] WordCountDelayed; logic BufferCaptureEn; @@ -79,17 +79,17 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer logic [WORDSPERLINE-1:0] CaptureWord; assign CaptureWord[index] = BufferCaptureEn & (index == WordCountDelayed); - flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(LSUBusHRDATA), + flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(HRDATA), .q(DLSUBusBuffer[(index+1)*`XLEN-1:index*`XLEN])); end - mux2 #(`PA_BITS) localadrmux(CacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr); - assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr; - mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), - .s(SelUncachedAdr), .y(LSUBusSize)); + mux2 #(`PA_BITS) localadrmux(CacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalHADDR); + assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR; + mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), + .s(SelUncachedAdr), .y(HSIZE)); busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( .clk, .reset, .IgnoreRequest, .LSURWM, .CacheFetchLine, .CacheWriteLine, - .LSUBusAck, .LSUBusInit, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .SelLSUBusWord, .LSUBusRead, + .BusAck, .BusInit, .CPUBusy, .CacheableM, .BusStall, .BusWrite, .SelLSUBusWord, .BusRead, .BufferCaptureEn, - .LSUBurstType, .LSUTransType, .LSUTransComplete, .CacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); + .HBURST, .HTRANS, .BusTransComplete, .CacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index f0204f3e4..e86f76788 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -40,18 +40,18 @@ module busfsm #(parameter integer WordCountThreshold, input logic [1:0] LSURWM, input logic CacheFetchLine, input logic CacheWriteLine, - input logic LSUBusAck, - input logic LSUBusInit, // This might be better as LSUBusLock, or to send this using LSUBusAck. + input logic BusAck, + input logic BusInit, // This might be better as LSUBusLock, or to send this using BusAck. input logic CPUBusy, input logic CacheableM, output logic BusStall, - output logic LSUBusWrite, + output logic BusWrite, output logic SelLSUBusWord, - output logic LSUBusRead, - output logic [2:0] LSUBurstType, - output logic LSUTransComplete, - output logic [1:0] LSUTransType, + output logic BusRead, + output logic [2:0] HBURST, + output logic BusTransComplete, + output logic [1:0] HTRANS, output logic CacheBusAck, output logic BusCommittedM, output logic SelUncachedAdr, @@ -60,8 +60,8 @@ module busfsm #(parameter integer WordCountThreshold, - logic UnCachedLSUBusRead; - logic UnCachedLSUBusWrite; + logic UnCachedBusRead; + logic UnCachedBusWrite; logic CntEn, PreCntEn; logic CntReset; logic WordCountFlag; @@ -103,7 +103,7 @@ module busfsm #(parameter integer WordCountThreshold, assign PreCntEn = (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); // Detect when we are waiting on the final access. - assign CntEn = (PreCntEn & LSUBusAck | (LSUBusInit)) & ~WordCountFlag & ~UnCachedRW; // Want to count when doing cache accesses and we aren't wrapping up. + assign CntEn = (PreCntEn & BusAck | (BusInit)) & ~WordCountFlag & ~UnCachedRW; // Want to count when doing cache accesses and we aren't wrapping up. assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM; @@ -119,9 +119,9 @@ module busfsm #(parameter integer WordCountThreshold, else if(CacheFetchLine) BusNextState = STATE_BUS_FETCH; else if(CacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; - STATE_BUS_UNCACHED_WRITE: if(LSUBusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; + STATE_BUS_UNCACHED_WRITE: if(BusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; else BusNextState = STATE_BUS_UNCACHED_WRITE; - STATE_BUS_UNCACHED_READ: if(LSUBusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE; + STATE_BUS_UNCACHED_READ: if(BusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE; else BusNextState = STATE_BUS_UNCACHED_READ; STATE_BUS_UNCACHED_WRITE_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; else BusNextState = STATE_BUS_READY; @@ -129,12 +129,12 @@ module busfsm #(parameter integer WordCountThreshold, else BusNextState = STATE_BUS_READY; STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; else BusNextState = STATE_BUS_READY; - STATE_BUS_FETCH: if (WordCountFlag & LSUBusAck) begin + STATE_BUS_FETCH: if (WordCountFlag & BusAck) begin if (CacheFetchLine) BusNextState = STATE_BUS_FETCH; else if (CacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; end else BusNextState = STATE_BUS_FETCH; - STATE_BUS_WRITE: if(WordCountFlag & LSUBusAck) begin + STATE_BUS_WRITE: if(WordCountFlag & BusAck) begin if (CacheFetchLine) BusNextState = STATE_BUS_FETCH; else if (CacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; @@ -153,35 +153,35 @@ module busfsm #(parameter integer WordCountThreshold, endcase end - assign LSUBurstType = (UnCachedRW) ? 3'b0 : LocalBurstType; // Don't want to use burst when doing an Uncached Access. - assign LSUTransComplete = (UnCachedRW) ? LSUBusAck : WordCountFlag & LSUBusAck; + assign HBURST = (UnCachedRW) ? 3'b0 : LocalBurstType; // Don't want to use burst when doing an Uncached Access. + assign BusTransComplete = (UnCachedRW) ? BusAck : WordCountFlag & BusAck; // Use SEQ if not doing first word, NONSEQ if doing the first read/write, and IDLE if finishing up. - assign LSUTransType = (|WordCount) & ~UnCachedRW ? AHB_SEQ : (LSUBusRead | LSUBusWrite) & (~LSUTransComplete) ? AHB_NONSEQ : AHB_IDLE; + assign HTRANS = (|WordCount) & ~UnCachedRW ? AHB_SEQ : (BusRead | BusWrite) & (~BusTransComplete) ? AHB_NONSEQ : AHB_IDLE; // Reset if we aren't initiating a transaction or if we are finishing a transaction. - assign CntReset = BusCurrState == STATE_BUS_READY & ~(CacheFetchLine | CacheWriteLine) | LSUTransComplete; + assign CntReset = BusCurrState == STATE_BUS_READY & ~(CacheFetchLine | CacheWriteLine) | BusTransComplete; assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | CacheFetchLine | CacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); - assign UnCachedLSUBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) | + assign UnCachedBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_WRITE); - assign LSUBusWrite = UnCachedLSUBusWrite | (BusCurrState == STATE_BUS_WRITE & ~WordCountFlag); + assign BusWrite = UnCachedBusWrite | (BusCurrState == STATE_BUS_WRITE & ~WordCountFlag); assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0]) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_WRITE); - assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) | + assign UnCachedBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_READ); - assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & CacheFetchLine); - assign BufferCaptureEn = UnCachedLSUBusRead | BusCurrState == STATE_BUS_FETCH; + assign BusRead = UnCachedBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & CacheFetchLine); + assign BufferCaptureEn = UnCachedBusRead | BusCurrState == STATE_BUS_FETCH; // Makes bus only do uncached reads/writes when we actually do uncached reads/writes. Needed because CacheableM is 0 when flushing cache. - assign UnCachedRW = UnCachedLSUBusWrite | UnCachedLSUBusRead; + assign UnCachedRW = UnCachedBusWrite | UnCachedBusRead; - assign CacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LSUBusAck) | - (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LSUBusAck); + assign CacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & BusAck) | + (BusCurrState == STATE_BUS_WRITE & WordCountFlag & BusAck); assign BusCommittedM = BusCurrState != STATE_BUS_READY; assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LSURWM & UnCachedAccess)) | (BusCurrState == STATE_BUS_UNCACHED_READ | diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 10f8060b6..514b165eb 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -65,16 +65,16 @@ module lsu ( // cpu hazard unit (trap) output logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM, // connect to ahb - (* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUBusAdr, + (* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUHADDR, (* mark_debug = "true" *) output logic LSUBusRead, (* mark_debug = "true" *) output logic LSUBusWrite, (* mark_debug = "true" *) input logic LSUBusAck, (* mark_debug = "true" *) input logic LSUBusInit, - (* mark_debug = "true" *) input logic [`XLEN-1:0] LSUBusHRDATA, + (* mark_debug = "true" *) input logic [`XLEN-1:0] LSUHRDATA, (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA, - (* mark_debug = "true" *) output logic [2:0] LSUBusSize, - (* mark_debug = "true" *) output logic [2:0] LSUBurstType, - (* mark_debug = "true" *) output logic [1:0] LSUTransType, + (* mark_debug = "true" *) output logic [2:0] LSUHSIZE, + (* mark_debug = "true" *) output logic [2:0] LSUHBURST, + (* mark_debug = "true" *) output logic [1:0] LSUHTRANS, (* mark_debug = "true" *) output logic LSUTransComplete, // page table walker input logic [`XLEN-1:0] SATP_REGW, // from csr @@ -198,9 +198,10 @@ module lsu ( // The LSU allows both a DTIM and bus with cache. However, the PMA decoding presently // use the same UNCORE_RAM_BASE addresss for both the DTIM and any RAM in the Uncore. + // *** becomes DTIM_RAM_BASE if (`DMEM) begin : dtim - dtim dtim(.clk, .reset, .LSURWM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM), //*** fix the dtim FinalWriteData - is this done already? + dtim dtim(.clk, .reset, .LSURWM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM), .ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]), .Cacheable(CacheableM)); // since we have a local memory the bus connections are all disabled. @@ -223,9 +224,10 @@ module lsu ( busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) busdp( .clk, .reset, - .LSUBusHRDATA, .LSUBusAck, .LSUBusInit, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete, + .HRDATA(LSUHRDATA), .BusAck(LSUBusAck), .BusInit(LSUBusInit), .BusWrite(LSUBusWrite), + .BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), .WordCount, .SelLSUBusWord, - .LSUFunct3M, .LSUBusAdr, .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), + .LSUFunct3M, .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .DLSUBusBuffer, .LSUPAdrM, .SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .BusStall, .BusCommittedM); diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index db6da30b0..affcd5af2 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -145,11 +145,11 @@ module wallypipelinedcore ( logic IFUTransComplete; // AHB LSU interface - logic [`PA_BITS-1:0] LSUBusAdr; + logic [`PA_BITS-1:0] LSUHADDR; logic LSUBusRead; logic LSUBusWrite; logic LSUBusAck, LSUBusInit; - logic [`XLEN-1:0] LSUBusHRDATA; + logic [`XLEN-1:0] LSUHRDATA; logic [`XLEN-1:0] LSUBusHWDATA; logic BPPredWrongE; @@ -159,9 +159,9 @@ module wallypipelinedcore ( logic BPPredClassNonCFIWrongM; logic [4:0] InstrClassM; logic InstrAccessFaultF; - logic [2:0] LSUBusSize; - logic [2:0] LSUBurstType; - logic [1:0] LSUTransType; + logic [2:0] LSUHSIZE; + logic [2:0] LSUHBURST; + logic [1:0] LSUHTRANS; logic LSUTransComplete; logic DCacheMiss; @@ -263,8 +263,8 @@ module wallypipelinedcore ( .IEUAdrE, .IEUAdrM, .WriteDataM, .ReadDataW, .FlushDCacheM, // connected to ahb (all stay the same) - .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit, - .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete, + .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit, + .LSUHRDATA, .LSUBusHWDATA, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete, // connect to csr or privilege and stay the same. .PrivilegeModeW, .BigEndianM, // connects to csr @@ -303,11 +303,11 @@ module wallypipelinedcore ( .IFUBusAck, .IFUBusInit, // Signals from Data Cache - .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA, - .LSUBusHRDATA, - .LSUBusSize, - .LSUBurstType, - .LSUTransType, + .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA, + .LSUHRDATA, + .LSUHSIZE, + .LSUHBURST, + .LSUHTRANS, .LSUTransComplete, .LSUBusAck, .LSUBusInit, From 5dc4fb757af778abd918f02da633d0ce7aa3964c Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Aug 2022 10:20:02 -0700 Subject: [PATCH 05/10] Continued busdp/ebu simplification --- pipelined/src/ebu/ahblite.sv | 41 ++++++++----------- pipelined/src/ifu/ifu.sv | 14 +++---- pipelined/src/ifu/irom.sv | 48 +++++++++++++++++++++++ pipelined/src/lsu/lsu.sv | 12 +++--- pipelined/src/wally/wallypipelinedcore.sv | 28 ++++++------- 5 files changed, 90 insertions(+), 53 deletions(-) create mode 100644 pipelined/src/ifu/irom.sv diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 6c3d0c330..8d2a58f19 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -41,29 +41,27 @@ module ahblite ( input logic UnsignedLoadM, input logic [1:0] AtomicMaskedM, // Signals from Instruction Cache - input logic [`PA_BITS-1:0] IFUBusAdr, + input logic [`PA_BITS-1:0] IFUHADDR, + input logic [2:0] IFUHBURST, + input logic [1:0] IFUHTRANS, input logic IFUBusRead, - output logic [`XLEN-1:0] IFUBusHRDATA, - output logic IFUBusAck, - output logic IFUBusInit, - input logic [2:0] IFUBurstType, - input logic [1:0] IFUTransType, input logic IFUTransComplete, + output logic IFUBusInit, + output logic IFUBusAck, // Signals from Data Cache input logic [`PA_BITS-1:0] LSUHADDR, - input logic LSUBusRead, - input logic LSUBusWrite, - input logic [`XLEN-1:0] LSUBusHWDATA, - output logic [`XLEN-1:0] LSUHRDATA, + input logic [`XLEN-1:0] LSUHWDATA, input logic [2:0] LSUHSIZE, input logic [2:0] LSUHBURST, input logic [1:0] LSUHTRANS, + input logic LSUBusRead, + input logic LSUBusWrite, input logic LSUTransComplete, - output logic LSUBusAck, output logic LSUBusInit, + output logic LSUBusAck, + // AHB-Lite external signals - (* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA, (* mark_debug = "true" *) input logic HREADY, HRESP, (* mark_debug = "true" *) output logic HCLK, HRESETn, (* mark_debug = "true" *) output logic [31:0] HADDR, // *** one day switch to a different bus that supports the full physical address @@ -86,8 +84,7 @@ module ahblite ( logic LSUGrant; logic [31:0] AccessAddress; - logic [2:0] ISize; - + assign HCLK = clk; assign HRESETn = ~reset; @@ -133,11 +130,10 @@ module ahblite ( // bus outputs assign #1 LSUGrant = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); - assign AccessAddress = (LSUGrant) ? LSUHADDR[31:0] : IFUBusAdr[31:0]; + assign AccessAddress = LSUGrant ? LSUHADDR[31:0] : IFUHADDR[31:0]; assign HADDR = AccessAddress; - assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway - assign HSIZE = (LSUGrant) ? {1'b0, LSUHSIZE[1:0]} : ISize; - assign HBURST = (LSUGrant) ? LSUHBURST : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst. + assign HSIZE = LSUGrant ? {1'b0, LSUHSIZE[1:0]} : 3'b010; // Instruction reads are always 32 bits + assign HBURST = LSUGrant ? LSUHBURST : IFUHBURST; // If doing memory accesses, use LSUburst, else use Instruction burst. /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE. 000: Single (SINGLE) @@ -153,23 +149,20 @@ module ahblite ( assign HPROT = 4'b0011; // not used; see Section 3.7 - assign HTRANS = (LSUGrant) ? LSUHTRANS : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise + assign HTRANS = LSUGrant ? LSUHTRANS : IFUHTRANS; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HMASTLOCK = 0; // no locking supported assign HWRITE = (NextBusState == MEMWRITE); // Byte mask for HWSTRB swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(HWSTRB)); // delay write data by one cycle for - flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN + flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN // delay signals for subword writes flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD); flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED); flop #(1) writereg(HCLK, HWRITE, HWRITED); - // Route signals to Instruction and Data Caches - // *** assumes AHBW = XLEN - assign IFUBusHRDATA = HRDATA; - assign LSUHRDATA = HRDATA; + // Send control back to IFU and LSU assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD); assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState != MEMWRITE) & (NextBusState == MEMWRITE)); assign IFUBusAck = HREADY & (BusState == INSTRREAD); diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 1f3bda8c6..1c21bbbfc 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -36,14 +36,14 @@ module ifu ( input logic StallF, StallD, StallE, StallM, input logic FlushF, FlushD, FlushE, FlushM, // Bus interface -(* mark_debug = "true" *) input logic [`XLEN-1:0] IFUBusHRDATA, +(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, (* mark_debug = "true" *) input logic IFUBusAck, (* mark_debug = "true" *) input logic IFUBusInit, -(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUBusAdr, +(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR, (* mark_debug = "true" *) output logic IFUBusRead, (* mark_debug = "true" *) output logic IFUStallF, -(* mark_debug = "true" *) output logic [2:0] IFUBurstType, -(* mark_debug = "true" *) output logic [1:0] IFUTransType, +(* mark_debug = "true" *) output logic [2:0] IFUHBURST, +(* mark_debug = "true" *) output logic [1:0] IFUHTRANS, (* mark_debug = "true" *) output logic IFUTransComplete, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, // Execute @@ -203,9 +203,9 @@ module ifu ( busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) busdp(.clk, .reset, - .HRDATA(IFUBusHRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelLSUBusWord(), - .BusRead(IFUBusRead), .HSIZE(), .HBURST(IFUBurstType), .HTRANS(IFUTransType), .BusTransComplete(IFUTransComplete), - .LSUFunct3M(3'b010), .HADDR(IFUBusAdr), .CacheBusAdr(ICacheBusAdr), + .HRDATA(HRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelLSUBusWord(), + .BusRead(IFUBusRead), .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .BusTransComplete(IFUTransComplete), + .LSUFunct3M(3'b010), .HADDR(IFUHADDR), .CacheBusAdr(ICacheBusAdr), .WordCount(), .CacheFetchLine(ICacheFetchLine), .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck), diff --git a/pipelined/src/ifu/irom.sv b/pipelined/src/ifu/irom.sv new file mode 100644 index 000000000..fccc916d9 --- /dev/null +++ b/pipelined/src/ifu/irom.sv @@ -0,0 +1,48 @@ +/////////////////////////////////////////// +// irom.sv +// +// Written: Ross Thompson ross1728@gmail.com January 30, 2022 +// Modified: +// +// Purpose: simple instruction ROM +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module irom( + input logic clk, reset, + input logic [1:0] LSURWM, + input logic [`XLEN-1:0] IEUAdrE, + input logic TrapM, + output logic [`LLEN-1:0] ReadDataWordM +); + + +// localparam ADDR_WDITH = $clog2(`IROM_RAM_RANGE/8); // *** replace with tihs when defined + localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size + localparam OFFSET = $clog2(`LLEN/8); + + brom1p1rw #(`LLEN/8, 8, ADDR_WDITH) + rom(.clk, .addr(IEUAdrE[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM)); +endmodule + diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 514b165eb..06dac3555 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -70,8 +70,8 @@ module lsu ( (* mark_debug = "true" *) output logic LSUBusWrite, (* mark_debug = "true" *) input logic LSUBusAck, (* mark_debug = "true" *) input logic LSUBusInit, - (* mark_debug = "true" *) input logic [`XLEN-1:0] LSUHRDATA, - (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA, + (* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, + (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUHWDATA, (* mark_debug = "true" *) output logic [2:0] LSUHSIZE, (* mark_debug = "true" *) output logic [2:0] LSUHBURST, (* mark_debug = "true" *) output logic [1:0] LSUHTRANS, @@ -224,7 +224,7 @@ module lsu ( busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) busdp( .clk, .reset, - .HRDATA(LSUHRDATA), .BusAck(LSUBusAck), .BusInit(LSUBusInit), .BusWrite(LSUBusWrite), + .HRDATA, .BusAck(LSUBusAck), .BusInit(LSUBusInit), .BusWrite(LSUBusWrite), .BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), .WordCount, .SelLSUBusWord, .LSUFunct3M, .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), @@ -234,8 +234,8 @@ module lsu ( mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, DLSUBusBuffer[`XLEN-1:0]}), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); - mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]), - .s(SelUncachedAdr), .y(LSUBusHWDATA)); + mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]), + .s(SelUncachedAdr), .y(LSUHWDATA)); if(`DCACHE) begin : dcache cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( @@ -254,7 +254,7 @@ module lsu ( assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM; end end else begin: nobus // block: bus - assign {LSUBusHWDATA, SelUncachedAdr} = '0; + assign {LSUHWDATA, SelUncachedAdr} = '0; assign ReadDataWordMuxM = LittleEndianReadDataWordM; end diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 5fc8904f9..4b2f4d11d 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -136,12 +136,11 @@ module wallypipelinedcore ( logic CommittedM; // AHB ifu interface - logic [`PA_BITS-1:0] IFUBusAdr; - logic [`XLEN-1:0] IFUBusHRDATA; + logic [`PA_BITS-1:0] IFUHADDR; logic IFUBusRead; logic IFUBusAck, IFUBusInit; - logic [2:0] IFUBurstType; - logic [1:0] IFUTransType; + logic [2:0] IFUHBURST; + logic [1:0] IFUHTRANS; logic IFUTransComplete; // AHB LSU interface @@ -149,8 +148,7 @@ module wallypipelinedcore ( logic LSUBusRead; logic LSUBusWrite; logic LSUBusAck, LSUBusInit; - logic [`XLEN-1:0] LSUHRDATA; - logic [`XLEN-1:0] LSUBusHWDATA; + logic [`XLEN-1:0] LSUHWDATA; logic BPPredWrongE; logic BPPredDirWrongM; @@ -178,8 +176,8 @@ module wallypipelinedcore ( .StallF, .StallD, .StallE, .StallM, .FlushF, .FlushD, .FlushE, .FlushM, // Fetch - .IFUBusHRDATA, .IFUBusAck, .IFUBusInit, .PCF, .IFUBusAdr, - .IFUBusRead, .IFUStallF, .IFUBurstType, .IFUTransType, .IFUTransComplete, + .HRDATA, .IFUBusAck, .IFUBusInit, .PCF, .IFUHADDR, + .IFUBusRead, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUTransComplete, .ICacheAccess, .ICacheMiss, // Execute @@ -264,7 +262,7 @@ module wallypipelinedcore ( .ReadDataW, .FlushDCacheM, // connected to ahb (all stay the same) .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit, - .LSUHRDATA, .LSUBusHWDATA, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete, + .HRDATA, .LSUHWDATA, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete, // connect to csr or privilege and stay the same. .PrivilegeModeW, .BigEndianM, // connects to csr @@ -296,16 +294,14 @@ module wallypipelinedcore ( ahblite ebu(// IFU connections .clk, .reset, .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), - .IFUBusAdr, .IFUBusRead, - .IFUBusHRDATA, - .IFUBurstType, - .IFUTransType, + .IFUHADDR, .IFUBusRead, + .IFUHBURST, + .IFUHTRANS, .IFUTransComplete, .IFUBusAck, .IFUBusInit, // Signals from Data Cache - .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA, - .LSUHRDATA, + .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUHWDATA, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, @@ -313,7 +309,7 @@ module wallypipelinedcore ( .LSUBusAck, .LSUBusInit, - .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, + .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED, .HWRITED); From cd02c894dfc5035102e1ccf4cba3b433e4ef47f6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Aug 2022 10:44:39 -0700 Subject: [PATCH 06/10] renamed BusBuffer to FetchBuffer --- pipelined/src/cache/cache.sv | 9 ++++----- pipelined/src/ebu/ahblite.sv | 6 ++---- pipelined/src/ifu/ifu.sv | 8 ++++---- pipelined/src/lsu/busdp.sv | 6 +++--- pipelined/src/lsu/lsu.sv | 8 ++++---- 5 files changed, 17 insertions(+), 20 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index fd71e6526..9558cca2d 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -58,7 +58,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE input logic CacheBusAck, input logic SelLSUBusWord, input logic [LOGBWPL-1:0] WordCount, - input logic [LINELEN-1:0] LSUBusBuffer, + input logic [LINELEN-1:0] FetchBuffer, output logic [`PA_BITS-1:0] CacheBusAdr, output logic [WORDLEN-1:0] ReadDataWord); @@ -150,7 +150,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE .y(WordOffsetAddr)); else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]; - mux2 #(LINELEN) EarlyReturnMux(ReadDataLineCache, LSUBusBuffer, SelBusBuffer, ReadDataLine); + mux2 #(LINELEN) EarlyReturnMux(ReadDataLineCache, FetchBuffer, SelBusBuffer, ReadDataLine); subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL) subcachelineread( .PAdr(WordOffsetAddr), @@ -173,10 +173,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE for(index = 0; index < LINELEN/8; index++) begin mux2 #(8) WriteDataMux(.d0(FinalWriteDataDup[8*index+7:8*index]), - .d1(LSUBusBuffer[8*index+7:8*index]), .s(LineByteMux[index]), .y(CacheWriteData[8*index+7:8*index])); + .d1(FetchBuffer[8*index+7:8*index]), .s(LineByteMux[index]), .y(CacheWriteData[8*index+7:8*index])); end - //mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}), -// .d1(LSUBusBuffer), .s(SetValid), .y(CacheWriteData)); + mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), .d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), .d2({VictimTag, FlushAdr, {OFFSETLEN{1'b0}}}), diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 8d2a58f19..e41a31d10 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -83,7 +83,6 @@ module ahblite ( statetype BusState, NextBusState; logic LSUGrant; - logic [31:0] AccessAddress; assign HCLK = clk; assign HRESETn = ~reset; @@ -128,10 +127,9 @@ module ahblite ( endcase - // bus outputs + // LSU/IFU mux: choose source of access assign #1 LSUGrant = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); - assign AccessAddress = LSUGrant ? LSUHADDR[31:0] : IFUHADDR[31:0]; - assign HADDR = AccessAddress; + assign HADDR = LSUGrant ? LSUHADDR[31:0] : IFUHADDR[31:0]; assign HSIZE = LSUGrant ? {1'b0, LSUHSIZE[1:0]} : 3'b010; // Instruction reads are always 32 bits assign HBURST = LSUGrant ? LSUHBURST : IFUHBURST; // If doing memory accesses, use LSUburst, else use Instruction burst. diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 1c21bbbfc..442d23d29 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -196,7 +196,7 @@ module ifu ( localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN; localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; - logic [LINELEN-1:0] ILSUBusBuffer; + logic [LINELEN-1:0] FetchBuffer; logic [`PA_BITS-1:0] ICacheBusAdr; logic ICacheBusAck; logic SelUncachedAdr; @@ -209,13 +209,13 @@ module ifu ( .WordCount(), .CacheFetchLine(ICacheFetchLine), .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck), - .DLSUBusBuffer(ILSUBusBuffer), .LSUPAdrM(PCPF), + .FetchBuffer, .LSUPAdrM(PCPF), .SelUncachedAdr, .IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF), .BusStall, .BusCommittedM()); - mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(ILSUBusBuffer[32-1:0]), + mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]), .s(SelUncachedAdr), .y(AllInstrRawF[31:0])); @@ -224,7 +224,7 @@ module ifu ( .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM, - .LSUBusBuffer(ILSUBusBuffer), .CacheBusAck(ICacheBusAck), + .FetchBuffer, .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheFetchLine(ICacheFetchLine), .CacheWriteLine(), .ReadDataWord(FinalInstrRawF), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 0f0e2b47a..cb216e718 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -46,7 +46,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) output logic BusRead, output logic [2:0] HSIZE, output logic [2:0] HBURST, - output logic [1:0] HTRANS, // For AHBLite + output logic [1:0] HTRANS, output logic BusTransComplete, output logic [`PA_BITS-1:0] HADDR, output logic [LOGWPL-1:0] WordCount, @@ -56,7 +56,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) input logic CacheFetchLine, input logic CacheWriteLine, output logic CacheBusAck, - output logic [LINELEN-1:0] DLSUBusBuffer, //*** change name. + output logic [LINELEN-1:0] FetchBuffer, output logic SelUncachedAdr, // lsu/ifu interface @@ -80,7 +80,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) logic [WORDSPERLINE-1:0] CaptureWord; assign CaptureWord[index] = BufferCaptureEn & (index == WordCountDelayed); flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(HRDATA), - .q(DLSUBusBuffer[(index+1)*`XLEN-1:index*`XLEN])); + .q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN])); end mux2 #(`PA_BITS) localadrmux(CacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalHADDR); assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 06dac3555..5ec268223 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -215,7 +215,7 @@ module lsu ( localparam integer WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN; localparam integer LOGBWPL = `DCACHE ? $clog2(WORDSPERLINE) : 1; - logic [LINELEN-1:0] DLSUBusBuffer; + logic [LINELEN-1:0] FetchBuffer; logic [`PA_BITS-1:0] DCacheBusAdr; logic DCacheWriteLine; logic DCacheFetchLine; @@ -228,11 +228,11 @@ module lsu ( .BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), .WordCount, .SelLSUBusWord, .LSUFunct3M, .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), - .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .DLSUBusBuffer, .LSUPAdrM, + .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .LSUPAdrM, .SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .BusStall, .BusCommittedM); - mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, DLSUBusBuffer[`XLEN-1:0]}), + mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]), .s(SelUncachedAdr), .y(LSUHWDATA)); @@ -246,7 +246,7 @@ module lsu ( .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .IgnoreRequestTLB, .TrapM, .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM), - .LSUBusBuffer(DLSUBusBuffer), .CacheFetchLine(DCacheFetchLine), + .FetchBuffer, .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); end else begin : passthrough From 78618f5fc0b1477ac21c27a5e499f003c74bacb7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Aug 2022 11:05:10 -0700 Subject: [PATCH 07/10] Renaming LSU signals from busdp --- pipelined/src/ifu/ifu.sv | 10 ++++------ pipelined/src/ifu/irom.sv | 10 ++++------ pipelined/src/lsu/busdp.sv | 18 +++++++++--------- pipelined/src/lsu/busfsm.sv | 16 ++++++++-------- pipelined/src/lsu/lsu.sv | 4 ++-- 5 files changed, 27 insertions(+), 31 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 442d23d29..aab3ad00d 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -184,10 +184,8 @@ module ifu ( logic [`XLEN-1:0] AllInstrRawF; assign InstrRawF = AllInstrRawF[31:0]; - if (`IROM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM - irom irom(.clk, .reset, .LSURWM(2'b10), .IEUAdrE(PCNextFSpill), - .TrapM(1'b0), - .ReadDataWordM({{(`XLEN-32){1'b0}}, FinalInstrRawF})); + if (`IROM) begin : irom + irom irom(.clk, .reset, .Adr(PCNextFSpill), .ReadData(FinalInstrRawF)); assign {BusStall, IFUBusRead} = '0; assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0; @@ -209,9 +207,9 @@ module ifu ( .WordCount(), .CacheFetchLine(ICacheFetchLine), .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck), - .FetchBuffer, .LSUPAdrM(PCPF), + .FetchBuffer, .PAdrM(PCPF), .SelUncachedAdr, - .IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF), + .IgnoreRequest(ITLBMissF), .RWM(2'b10), .CPUBusy, .CacheableM(CacheableF), .BusStall, .BusCommittedM()); diff --git a/pipelined/src/ifu/irom.sv b/pipelined/src/ifu/irom.sv index fccc916d9..83585c07e 100644 --- a/pipelined/src/ifu/irom.sv +++ b/pipelined/src/ifu/irom.sv @@ -31,10 +31,8 @@ module irom( input logic clk, reset, - input logic [1:0] LSURWM, - input logic [`XLEN-1:0] IEUAdrE, - input logic TrapM, - output logic [`LLEN-1:0] ReadDataWordM + input logic [`XLEN-1:0] Adr, + output logic [31:0] ReadData ); @@ -42,7 +40,7 @@ module irom( localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size localparam OFFSET = $clog2(`LLEN/8); - brom1p1rw #(`LLEN/8, 8, ADDR_WDITH) - rom(.clk, .addr(IEUAdrE[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM)); + brom1p1rw #(ADDR_WDITH, 32) + rom(.clk, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadData)); endmodule diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index cb216e718..8da148abb 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -60,9 +60,9 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) output logic SelUncachedAdr, // lsu/ifu interface - input logic [`PA_BITS-1:0] LSUPAdrM, + input logic [`PA_BITS-1:0] PAdrM, input logic IgnoreRequest, - input logic [1:0] LSURWM, + input logic [1:0] RWM, input logic CPUBusy, input logic CacheableM, input logic [2:0] LSUFunct3M, @@ -75,21 +75,21 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) logic [LOGWPL-1:0] WordCountDelayed; logic BufferCaptureEn; - genvar index; + genvar index; for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer logic [WORDSPERLINE-1:0] CaptureWord; assign CaptureWord[index] = BufferCaptureEn & (index == WordCountDelayed); flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(HRDATA), .q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN])); end - mux2 #(`PA_BITS) localadrmux(CacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalHADDR); + + mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdrM, SelUncachedAdr, LocalHADDR); assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR; - mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), - .s(SelUncachedAdr), .y(HSIZE)); + + mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(HSIZE)); busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( - .clk, .reset, .IgnoreRequest, .LSURWM, .CacheFetchLine, .CacheWriteLine, - .BusAck, .BusInit, .CPUBusy, .CacheableM, .BusStall, .BusWrite, .SelLSUBusWord, .BusRead, - .BufferCaptureEn, + .clk, .reset, .IgnoreRequest, .RWM, .CacheFetchLine, .CacheWriteLine, + .BusAck, .BusInit, .CPUBusy, .CacheableM, .BusStall, .BusWrite, .SelLSUBusWord, .BusRead, .BufferCaptureEn, .HBURST, .HTRANS, .BusTransComplete, .CacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index e86f76788..f95f77dd0 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -37,7 +37,7 @@ module busfsm #(parameter integer WordCountThreshold, input logic reset, input logic IgnoreRequest, - input logic [1:0] LSURWM, + input logic [1:0] RWM, input logic CacheFetchLine, input logic CacheWriteLine, input logic BusAck, @@ -114,8 +114,8 @@ module busfsm #(parameter integer WordCountThreshold, always_comb begin case(BusCurrState) STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; - else if(LSURWM[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE; - else if(LSURWM[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ; + else if(RWM[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE; + else if(RWM[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ; else if(CacheFetchLine) BusNextState = STATE_BUS_FETCH; else if(CacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; @@ -160,19 +160,19 @@ module busfsm #(parameter integer WordCountThreshold, // Reset if we aren't initiating a transaction or if we are finishing a transaction. assign CntReset = BusCurrState == STATE_BUS_READY & ~(CacheFetchLine | CacheWriteLine) | BusTransComplete; - assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | CacheFetchLine | CacheWriteLine)) | + assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|RWM)) | CacheFetchLine | CacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); - assign UnCachedBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) | + assign UnCachedBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RWM[0] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_WRITE); assign BusWrite = UnCachedBusWrite | (BusCurrState == STATE_BUS_WRITE & ~WordCountFlag); - assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0]) | + assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RWM[0]) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_WRITE); - assign UnCachedBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) | + assign UnCachedBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RWM[1] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_READ); assign BusRead = UnCachedBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & CacheFetchLine); assign BufferCaptureEn = UnCachedBusRead | BusCurrState == STATE_BUS_FETCH; @@ -183,7 +183,7 @@ module busfsm #(parameter integer WordCountThreshold, assign CacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & BusAck) | (BusCurrState == STATE_BUS_WRITE & WordCountFlag & BusAck); assign BusCommittedM = BusCurrState != STATE_BUS_READY; - assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LSURWM & UnCachedAccess)) | + assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|RWM & UnCachedAccess)) | (BusCurrState == STATE_BUS_UNCACHED_READ | BusCurrState == STATE_BUS_UNCACHED_READ_DONE | BusCurrState == STATE_BUS_UNCACHED_WRITE | diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 5ec268223..92b82d817 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -228,8 +228,8 @@ module lsu ( .BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), .WordCount, .SelLSUBusWord, .LSUFunct3M, .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), - .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .LSUPAdrM, - .SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, + .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdrM(LSUPAdrM), + .SelUncachedAdr, .IgnoreRequest, .RWM(LSURWM), .CPUBusy, .CacheableM, .BusStall, .BusCommittedM); mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}), From 84ba62a04c2326546c7bc9a24e6993f95ffddc86 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Aug 2022 11:08:12 -0700 Subject: [PATCH 08/10] Renamed LSUFunct3M to Funct3 in busdp --- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/busdp.sv | 4 ++-- pipelined/src/lsu/lsu.sv | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index aab3ad00d..012e67a98 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -203,7 +203,7 @@ module ifu ( busdp(.clk, .reset, .HRDATA(HRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelLSUBusWord(), .BusRead(IFUBusRead), .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .BusTransComplete(IFUTransComplete), - .LSUFunct3M(3'b010), .HADDR(IFUHADDR), .CacheBusAdr(ICacheBusAdr), + .Funct3(3'b010), .HADDR(IFUHADDR), .CacheBusAdr(ICacheBusAdr), .WordCount(), .CacheFetchLine(ICacheFetchLine), .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 8da148abb..658438093 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -65,7 +65,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) input logic [1:0] RWM, input logic CPUBusy, input logic CacheableM, - input logic [2:0] LSUFunct3M, + input logic [2:0] Funct3, output logic SelLSUBusWord, output logic BusStall, output logic BusCommittedM); @@ -86,7 +86,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdrM, SelUncachedAdr, LocalHADDR); assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR; - mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(HSIZE)); + mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE)); busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( .clk, .reset, .IgnoreRequest, .RWM, .CacheFetchLine, .CacheWriteLine, diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 92b82d817..1028a1e7a 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -227,7 +227,7 @@ module lsu ( .HRDATA, .BusAck(LSUBusAck), .BusInit(LSUBusInit), .BusWrite(LSUBusWrite), .BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), .WordCount, .SelLSUBusWord, - .LSUFunct3M, .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), + .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdrM(LSUPAdrM), .SelUncachedAdr, .IgnoreRequest, .RWM(LSURWM), .CPUBusy, .CacheableM, .BusStall, .BusCommittedM); From 7a129af9adae833912b8515ddfd28120ae96534a Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Aug 2022 11:13:01 -0700 Subject: [PATCH 09/10] Removed M sufix from busdp signals --- pipelined/src/ifu/ifu.sv | 6 +++--- pipelined/src/lsu/busdp.sv | 16 ++++++++-------- pipelined/src/lsu/busfsm.sv | 26 +++++++++++++------------- pipelined/src/lsu/lsu.sv | 6 +++--- 4 files changed, 27 insertions(+), 27 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 012e67a98..9bd5ea1f4 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -207,10 +207,10 @@ module ifu ( .WordCount(), .CacheFetchLine(ICacheFetchLine), .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck), - .FetchBuffer, .PAdrM(PCPF), + .FetchBuffer, .PAdr(PCPF), .SelUncachedAdr, - .IgnoreRequest(ITLBMissF), .RWM(2'b10), .CPUBusy, .CacheableM(CacheableF), - .BusStall, .BusCommittedM()); + .IgnoreRequest(ITLBMissF), .RW(2'b10), .CPUBusy, .Cacheable(CacheableF), + .BusStall, .BusCommitted()); mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 658438093..448fd3139 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -60,15 +60,15 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) output logic SelUncachedAdr, // lsu/ifu interface - input logic [`PA_BITS-1:0] PAdrM, + input logic [`PA_BITS-1:0] PAdr, input logic IgnoreRequest, - input logic [1:0] RWM, + input logic [1:0] RW, input logic CPUBusy, - input logic CacheableM, + input logic Cacheable, input logic [2:0] Funct3, output logic SelLSUBusWord, output logic BusStall, - output logic BusCommittedM); + output logic BusCommitted); localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; logic [`PA_BITS-1:0] LocalHADDR; @@ -83,13 +83,13 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) .q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN])); end - mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdrM, SelUncachedAdr, LocalHADDR); + mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdr, SelUncachedAdr, LocalHADDR); assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR; mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE)); busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( - .clk, .reset, .IgnoreRequest, .RWM, .CacheFetchLine, .CacheWriteLine, - .BusAck, .BusInit, .CPUBusy, .CacheableM, .BusStall, .BusWrite, .SelLSUBusWord, .BusRead, .BufferCaptureEn, - .HBURST, .HTRANS, .BusTransComplete, .CacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); + .clk, .reset, .IgnoreRequest, .RW, .CacheFetchLine, .CacheWriteLine, + .BusAck, .BusInit, .CPUBusy, .Cacheable, .BusStall, .BusWrite, .SelLSUBusWord, .BusRead, .BufferCaptureEn, + .HBURST, .HTRANS, .BusTransComplete, .CacheBusAck, .BusCommitted, .SelUncachedAdr, .WordCount, .WordCountDelayed); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index f95f77dd0..72a17d94f 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -37,13 +37,13 @@ module busfsm #(parameter integer WordCountThreshold, input logic reset, input logic IgnoreRequest, - input logic [1:0] RWM, + input logic [1:0] RW, input logic CacheFetchLine, input logic CacheWriteLine, input logic BusAck, input logic BusInit, // This might be better as LSUBusLock, or to send this using BusAck. input logic CPUBusy, - input logic CacheableM, + input logic Cacheable, output logic BusStall, output logic BusWrite, @@ -53,7 +53,7 @@ module busfsm #(parameter integer WordCountThreshold, output logic BusTransComplete, output logic [1:0] HTRANS, output logic CacheBusAck, - output logic BusCommittedM, + output logic BusCommitted, output logic SelUncachedAdr, output logic BufferCaptureEn, output logic [LOGWPL-1:0] WordCount, WordCountDelayed); @@ -105,7 +105,7 @@ module busfsm #(parameter integer WordCountThreshold, assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); // Detect when we are waiting on the final access. assign CntEn = (PreCntEn & BusAck | (BusInit)) & ~WordCountFlag & ~UnCachedRW; // Want to count when doing cache accesses and we aren't wrapping up. - assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM; + assign UnCachedAccess = ~CACHE_ENABLED | ~Cacheable; always_ff @(posedge clk) if (reset) BusCurrState <= #1 STATE_BUS_READY; @@ -114,8 +114,8 @@ module busfsm #(parameter integer WordCountThreshold, always_comb begin case(BusCurrState) STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; - else if(RWM[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE; - else if(RWM[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ; + else if(RW[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE; + else if(RW[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ; else if(CacheFetchLine) BusNextState = STATE_BUS_FETCH; else if(CacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; @@ -160,30 +160,30 @@ module busfsm #(parameter integer WordCountThreshold, // Reset if we aren't initiating a transaction or if we are finishing a transaction. assign CntReset = BusCurrState == STATE_BUS_READY & ~(CacheFetchLine | CacheWriteLine) | BusTransComplete; - assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|RWM)) | CacheFetchLine | CacheWriteLine)) | + assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|RW)) | CacheFetchLine | CacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); - assign UnCachedBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RWM[0] & ~IgnoreRequest) | + assign UnCachedBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RW[0] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_WRITE); assign BusWrite = UnCachedBusWrite | (BusCurrState == STATE_BUS_WRITE & ~WordCountFlag); - assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RWM[0]) | + assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RW[0]) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_WRITE); - assign UnCachedBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RWM[1] & ~IgnoreRequest) | + assign UnCachedBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RW[1] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_READ); assign BusRead = UnCachedBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & CacheFetchLine); assign BufferCaptureEn = UnCachedBusRead | BusCurrState == STATE_BUS_FETCH; - // Makes bus only do uncached reads/writes when we actually do uncached reads/writes. Needed because CacheableM is 0 when flushing cache. + // Makes bus only do uncached reads/writes when we actually do uncached reads/writes. Needed because Cacheable is 0 when flushing cache. assign UnCachedRW = UnCachedBusWrite | UnCachedBusRead; assign CacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & BusAck) | (BusCurrState == STATE_BUS_WRITE & WordCountFlag & BusAck); - assign BusCommittedM = BusCurrState != STATE_BUS_READY; - assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|RWM & UnCachedAccess)) | + assign BusCommitted = BusCurrState != STATE_BUS_READY; + assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|RW & UnCachedAccess)) | (BusCurrState == STATE_BUS_UNCACHED_READ | BusCurrState == STATE_BUS_UNCACHED_READ_DONE | BusCurrState == STATE_BUS_UNCACHED_WRITE | diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 1028a1e7a..e009feac2 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -228,9 +228,9 @@ module lsu ( .BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), .WordCount, .SelLSUBusWord, .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), - .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdrM(LSUPAdrM), - .SelUncachedAdr, .IgnoreRequest, .RWM(LSURWM), .CPUBusy, .CacheableM, - .BusStall, .BusCommittedM); + .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM), + .SelUncachedAdr, .IgnoreRequest, .RW(LSURWM), .CPUBusy, .Cacheable(CacheableM), + .BusStall, .BusCommitted(BusCommittedM)); mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); From d7be94fab2df3b10c28c80e67ae80d7ec98dc04d Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Aug 2022 11:18:13 -0700 Subject: [PATCH 10/10] Cleaned up SelBusWord --- pipelined/src/cache/cache.sv | 4 ++-- pipelined/src/ifu/ifu.sv | 4 ++-- pipelined/src/lsu/busdp.sv | 4 ++-- pipelined/src/lsu/busfsm.sv | 4 ++-- pipelined/src/lsu/lsu.sv | 6 +++--- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 9558cca2d..1e07bce68 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -56,7 +56,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE output logic CacheFetchLine, output logic CacheWriteLine, input logic CacheBusAck, - input logic SelLSUBusWord, + input logic SelBusWord, input logic [LOGBWPL-1:0] WordCount, input logic [LINELEN-1:0] FetchBuffer, output logic [`PA_BITS-1:0] CacheBusAdr, @@ -146,7 +146,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // like to fix this. if(DCACHE) mux2 #(LOGBWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]), - .d1(WordCount), .s(SelLSUBusWord), + .d1(WordCount), .s(SelBusWord), .y(WordOffsetAddr)); else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]; diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 9bd5ea1f4..8d81998c1 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -201,7 +201,7 @@ module ifu ( busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) busdp(.clk, .reset, - .HRDATA(HRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelLSUBusWord(), + .HRDATA(HRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelBusWord(), .BusRead(IFUBusRead), .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .BusTransComplete(IFUTransComplete), .Funct3(3'b010), .HADDR(IFUHADDR), .CacheBusAdr(ICacheBusAdr), .WordCount(), @@ -228,7 +228,7 @@ module ifu ( .CacheWriteLine(), .ReadDataWord(FinalInstrRawF), .Cacheable(CacheableF), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), - .ByteMask('0), .WordCount('0), .SelLSUBusWord('0), + .ByteMask('0), .WordCount('0), .SelBusWord('0), .FinalWriteData('0), .RW(2'b10), .Atomic('0), .FlushCache('0), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 448fd3139..825691443 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -66,7 +66,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) input logic CPUBusy, input logic Cacheable, input logic [2:0] Funct3, - output logic SelLSUBusWord, + output logic SelBusWord, output logic BusStall, output logic BusCommitted); @@ -90,6 +90,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( .clk, .reset, .IgnoreRequest, .RW, .CacheFetchLine, .CacheWriteLine, - .BusAck, .BusInit, .CPUBusy, .Cacheable, .BusStall, .BusWrite, .SelLSUBusWord, .BusRead, .BufferCaptureEn, + .BusAck, .BusInit, .CPUBusy, .Cacheable, .BusStall, .BusWrite, .SelBusWord, .BusRead, .BufferCaptureEn, .HBURST, .HTRANS, .BusTransComplete, .CacheBusAck, .BusCommitted, .SelUncachedAdr, .WordCount, .WordCountDelayed); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index 72a17d94f..2222decaf 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -47,7 +47,7 @@ module busfsm #(parameter integer WordCountThreshold, output logic BusStall, output logic BusWrite, - output logic SelLSUBusWord, + output logic SelBusWord, output logic BusRead, output logic [2:0] HBURST, output logic BusTransComplete, @@ -168,7 +168,7 @@ module busfsm #(parameter integer WordCountThreshold, assign UnCachedBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RW[0] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_WRITE); assign BusWrite = UnCachedBusWrite | (BusCurrState == STATE_BUS_WRITE & ~WordCountFlag); - assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RW[0]) | + assign SelBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RW[0]) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_WRITE); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index e009feac2..80e8399b3 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -108,7 +108,7 @@ module lsu ( logic InterlockStall; logic IgnoreRequestTLB; logic BusCommittedM, DCacheCommittedM; - logic SelLSUBusWord; + logic SelBusWord; logic DataDAPageFaultM; logic [`XLEN-1:0] IMWriteDataM, IMAWriteDataM; logic [`LLEN-1:0] IMAFWriteDataM; @@ -226,7 +226,7 @@ module lsu ( .clk, .reset, .HRDATA, .BusAck(LSUBusAck), .BusInit(LSUBusInit), .BusWrite(LSUBusWrite), .BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), - .WordCount, .SelLSUBusWord, + .WordCount, .SelBusWord, .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM), .SelUncachedAdr, .IgnoreRequest, .RW(LSURWM), .CPUBusy, .Cacheable(CacheableM), @@ -239,7 +239,7 @@ module lsu ( if(`DCACHE) begin : dcache cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( - .clk, .reset, .CPUBusy, .SelLSUBusWord, .RW(LSURWM), .Atomic(LSUAtomicM), + .clk, .reset, .CPUBusy, .SelBusWord, .RW(LSURWM), .Atomic(LSUAtomicM), .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), .ByteMask(ByteMaskM), .WordCount, .FinalWriteData(LSUWriteDataM), .Cacheable(CacheableM),