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Extend stall on leaf page lookups

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This commit is contained in:
Thomas Fleming 2021-04-22 01:51:38 -04:00
parent 939e36a151
commit 4d4ca24640
3 changed files with 18 additions and 4 deletions
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8
wally-pipelined/src/ebu/ahblite.sv
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@ -51,6 +51,7 @@ module ahblite (
input logic [`XLEN-1:0] WriteDataM, input logic [`XLEN-1:0] WriteDataM,
input logic [1:0] MemSizeM, input logic [1:0] MemSizeM,
// Signals from MMU // Signals from MMU
input logic MMUStall,
input logic [`XLEN-1:0] MMUPAdr, input logic [`XLEN-1:0] MMUPAdr,
input logic MMUTranslate, MMUTranslationComplete, input logic MMUTranslate, MMUTranslationComplete,
output logic [`XLEN-1:0] MMUReadPTE, output logic [`XLEN-1:0] MMUReadPTE,
@ -136,11 +137,10 @@ module ahblite (
// since translation might not be complete. // since translation might not be complete.
assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||
(NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) || (NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) ||
(NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete)); MMUStall);
// *** Could get finer grained stalling if we distinguish between MMU
// instruction address translation and data address translation
assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) || assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||
(NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete)); MMUStall);
// Determine access type (important for determining whether to fault) // Determine access type (important for determining whether to fault)
assign Atomic = ((NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE)); assign Atomic = ((NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE));

13
wally-pipelined/src/ebu/pagetablewalker.sv
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@ -60,6 +60,9 @@ module pagetablewalker (
output logic MMUTranslate, output logic MMUTranslate,
output logic MMUTranslationComplete, output logic MMUTranslationComplete,
// Stall signal
output logic MMUStall,
// Faults // Faults
output logic WalkerInstrPageFaultF, output logic WalkerInstrPageFaultF,
output logic WalkerLoadPageFaultM, output logic WalkerLoadPageFaultM,
@ -197,8 +200,12 @@ module pagetablewalker (
WalkerInstrPageFaultF = '0; WalkerInstrPageFaultF = '0;
WalkerLoadPageFaultM = '0; WalkerLoadPageFaultM = '0;
WalkerStorePageFaultM = '0; WalkerStorePageFaultM = '0;
MMUStall = '1;
case (NextWalkerState) case (NextWalkerState)
IDLE: begin
MMUStall = '0;
end
LEVEL1: begin LEVEL1: begin
TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
end end
@ -220,6 +227,7 @@ module pagetablewalker (
WalkerInstrPageFaultF = ~DTLBMissM; WalkerInstrPageFaultF = ~DTLBMissM;
WalkerLoadPageFaultM = DTLBMissM && ~MemStore; WalkerLoadPageFaultM = DTLBMissM && ~MemStore;
WalkerStorePageFaultM = DTLBMissM && MemStore; WalkerStorePageFaultM = DTLBMissM && MemStore;
MMUStall = '0; // Drop the stall early to enter trap handling code
end end
default: begin default: begin
// nothing // nothing
@ -302,8 +310,12 @@ module pagetablewalker (
WalkerInstrPageFaultF = '0; WalkerInstrPageFaultF = '0;
WalkerLoadPageFaultM = '0; WalkerLoadPageFaultM = '0;
WalkerStorePageFaultM = '0; WalkerStorePageFaultM = '0;
MMUStall = '1;
case (NextWalkerState) case (NextWalkerState)
IDLE: begin
MMUStall = '0;
end
LEVEL2: begin LEVEL2: begin
TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000}; TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000};
end end
@ -329,6 +341,7 @@ module pagetablewalker (
WalkerInstrPageFaultF = ~DTLBMissM; WalkerInstrPageFaultF = ~DTLBMissM;
WalkerLoadPageFaultM = DTLBMissM && ~MemStore; WalkerLoadPageFaultM = DTLBMissM && ~MemStore;
WalkerStorePageFaultM = DTLBMissM && MemStore; WalkerStorePageFaultM = DTLBMissM && MemStore;
MMUStall = '0; // Drop the stall early to enter trap handling code
end end
default: begin default: begin
// nothing // nothing

1
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -113,6 +113,7 @@ module wallypipelinedhart (
// IMem stalls // IMem stalls
logic ICacheStallF; logic ICacheStallF;
logic [`XLEN-1:0] MMUPAdr, MMUReadPTE; logic [`XLEN-1:0] MMUPAdr, MMUReadPTE;
logic MMUStall;
logic MMUTranslate, MMUTranslationComplete, MMUReady; logic MMUTranslate, MMUTranslationComplete, MMUReady;
// bus interface to dmem // bus interface to dmem