From 4d4ca246404a185b796a4592048e1642e19c8f01 Mon Sep 17 00:00:00 2001
From: Thomas Fleming <tfleming@hmc.edu>
Date: Thu, 22 Apr 2021 01:51:38 -0400
Subject: [PATCH] Extend stall on leaf page lookups

---
 wally-pipelined/src/ebu/ahblite.sv              |  8 ++++----
 wally-pipelined/src/ebu/pagetablewalker.sv      | 13 +++++++++++++
 wally-pipelined/src/wally/wallypipelinedhart.sv |  1 +
 3 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index 73b03599b..bd1caa9ff 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -51,6 +51,7 @@ module ahblite (
   input  logic [`XLEN-1:0] WriteDataM,
   input  logic [1:0]       MemSizeM,
   // Signals from MMU
+  input  logic             MMUStall,
   input  logic [`XLEN-1:0] MMUPAdr,
   input  logic             MMUTranslate, MMUTranslationComplete,
   output logic [`XLEN-1:0] MMUReadPTE,
@@ -136,11 +137,10 @@ module ahblite (
   // since translation might not be complete.
   assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || 
                     (NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) ||
-                    (NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete));
-  // *** Could get finer grained stalling if we distinguish between MMU
-  //     instruction address translation and data address translation
+                    MMUStall);
+
   assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||
-                          (NextBusState == MMUTRANSLATE) || (MMUTranslate && ~MMUTranslationComplete));
+                          MMUStall);
 
   // Determine access type (important for determining whether to fault)
   assign Atomic = ((NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE));
diff --git a/wally-pipelined/src/ebu/pagetablewalker.sv b/wally-pipelined/src/ebu/pagetablewalker.sv
index a1f10cd3e..e178154b8 100644
--- a/wally-pipelined/src/ebu/pagetablewalker.sv
+++ b/wally-pipelined/src/ebu/pagetablewalker.sv
@@ -60,6 +60,9 @@ module pagetablewalker (
   output logic             MMUTranslate,
   output logic             MMUTranslationComplete,
 
+  // Stall signal
+  output logic             MMUStall,
+
   // Faults
   output logic             WalkerInstrPageFaultF,
   output logic             WalkerLoadPageFaultM, 
@@ -197,8 +200,12 @@ module pagetablewalker (
         WalkerInstrPageFaultF = '0;
         WalkerLoadPageFaultM = '0;
         WalkerStorePageFaultM = '0;
+        MMUStall = '1;
 
         case (NextWalkerState)
+          IDLE: begin
+            MMUStall = '0;
+          end
           LEVEL1: begin
             TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
           end
@@ -220,6 +227,7 @@ module pagetablewalker (
             WalkerInstrPageFaultF = ~DTLBMissM;
             WalkerLoadPageFaultM = DTLBMissM && ~MemStore;
             WalkerStorePageFaultM = DTLBMissM && MemStore;
+            MMUStall = '0;  // Drop the stall early to enter trap handling code
           end
           default: begin
             // nothing
@@ -302,8 +310,12 @@ module pagetablewalker (
         WalkerInstrPageFaultF = '0;
         WalkerLoadPageFaultM = '0;
         WalkerStorePageFaultM = '0;
+        MMUStall = '1;
 
         case (NextWalkerState)
+          IDLE: begin
+            MMUStall = '0;
+          end
           LEVEL2: begin
             TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000};
           end
@@ -329,6 +341,7 @@ module pagetablewalker (
             WalkerInstrPageFaultF = ~DTLBMissM;
             WalkerLoadPageFaultM = DTLBMissM && ~MemStore;
             WalkerStorePageFaultM = DTLBMissM && MemStore;
+            MMUStall = '0;  // Drop the stall early to enter trap handling code
           end
           default: begin
             // nothing
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index ca474a756..a3487cbab 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -113,6 +113,7 @@ module wallypipelinedhart (
   // IMem stalls
   logic             ICacheStallF;
   logic [`XLEN-1:0] MMUPAdr, MMUReadPTE;
+  logic             MMUStall;
   logic             MMUTranslate, MMUTranslationComplete, MMUReady;
 
   // bus interface to dmem