diff --git a/fpga/src/axi_sdc_controller.v b/fpga/src/axi_sdc_controller.v index 28994182d..c32a6a783 100644 --- a/fpga/src/axi_sdc_controller.v +++ b/fpga/src/axi_sdc_controller.v @@ -205,7 +205,7 @@ always @(posedge clock) reset_sync <= {reset_sync[1:0], !async_resetn}; reg [7:0] clock_cnt; -reg clock_state; +(* mark_debug = "true" *) reg clock_state; (* mark_debug = "true" *) reg clock_posedge; reg clock_data_in; wire fifo_almost_full; @@ -265,7 +265,7 @@ wire sd_dat_oe; // IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t)); // IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t)); -always @(negedge clock) begin +always @(negedge sdio_clk) begin // Output data delayed by 1/2 clock cycle (5ns) to ensure // required hold time: default speed - min 5ns, high speed - min 2ns (actual 5ns) if (sdio_reset) begin diff --git a/linux/sdcard/flash-sd.sh b/linux/sdcard/flash-sd.sh index 9e00e0600..73c9e1b9e 100755 --- a/linux/sdcard/flash-sd.sh +++ b/linux/sdcard/flash-sd.sh @@ -56,7 +56,7 @@ done IMAGES=$BUILDROOT/output/images FW_JUMP=$IMAGES/fw_jump.bin LINUX_KERNEL=$IMAGES/Image -DEVICE_TREE=$IMAGES/$DEVICE_TREE +#DEVICE_TREE=$IMAGES/$DEVICE_TREE SDCARD=${ARGS[0]} diff --git a/sim/wally-imperas.do b/sim/wally-imperas.do index cc1c3845a..118e44d10 100644 --- a/sim/wally-imperas.do +++ b/sim/wally-imperas.do @@ -40,7 +40,7 @@ vlog +incdir+../config/$1 \ $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv \ ../src/cvw.sv \ - ../testbench/testbench_imperas.sv \ + ../testbench/testbench-imperas.sv \ ../testbench/common/*.sv \ ../src/*/*.sv \ ../src/*/*/*.sv \ diff --git a/testbench/testbench_imperas.sv b/testbench/testbench-imperas.sv similarity index 100% rename from testbench/testbench_imperas.sv rename to testbench/testbench-imperas.sv diff --git a/testbench/testbench-linux.sv b/testbench/testbench-linux.sv index 683f55952..54cfc66e4 100644 --- a/testbench/testbench-linux.sv +++ b/testbench/testbench-linux.sv @@ -27,7 +27,7 @@ `include "config.vh" import cvw::*; -`define DEBUG_TRACE 0 +`define DEBUG_TRACE 1 // Debug Levels // 0: don't check against QEMU // 1: print disagreements with QEMU, but only halt on PCW disagreements diff --git a/testbench/testbench-xcelium.sv b/testbench/testbench-xcelium.sv index f50259ca8..89a7cc995 100644 --- a/testbench/testbench-xcelium.sv +++ b/testbench/testbench-xcelium.sv @@ -265,9 +265,7 @@ module testbench; // declare memory labels that interest us, the updateProgramAddrLabelArray task will find // the addr of each label and fill the array. To expand, add more elements to this array // and initialize them to zero (also initilaize them to zero at the start of the next test) - if(!P.FPGA) begin - updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); - end + updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); end //////////////////////////////////////////////////////////////////////////////// @@ -361,21 +359,21 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// // load memories with program image //////////////////////////////////////////////////////////////////////////////// - if (P.FPGA) `define TB_FPGA // this is a gross hack for xcelium and verilator + if (P.SDC_SUPPORTED) `define TB_SDC_SUPPORTED // this is a gross hack for xcelium and verilator if (P.IROM_SUPPORTED) `define TB_IROM_SUPPORTED if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED if (P.BUS_SUPPORTED) `define TB_BUS_SUPPORTED always @(posedge clk) begin if (LoadMem) begin - if (P.FPGA) begin - `ifdef TB_FPGA + if (P.SDC_SUPPORTED) begin + `ifdef TB_SDC_SUPPORTED string romfilename, sdcfilename; romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; - $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM); - $readmemh(sdcfilename, sdcard.sdcard.FLASHmem); + //$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM); + //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem); // shorten sdc timers for simulation - dut.uncore.uncore.sdc.SDC.LimitTimers = 1; + //dut.uncore.uncore.sdc.SDC.LimitTimers = 1; `endif end else if (P.IROM_SUPPORTED) begin diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 74077e547..8635a4920 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -37,9 +37,9 @@ module testbench; parameter DEBUG=0; parameter TEST="none"; parameter PrintHPMCounters=1; - parameter BPRED_LOGGER=0; - parameter I_CACHE_ADDR_LOGGER=0; - parameter D_CACHE_ADDR_LOGGER=0; + parameter BPRED_LOGGER=1; + parameter I_CACHE_ADDR_LOGGER=1; + parameter D_CACHE_ADDR_LOGGER=1; `include "parameter-defs.vh" @@ -260,9 +260,7 @@ module testbench; // declare memory labels that interest us, the updateProgramAddrLabelArray task will find // the addr of each label and fill the array. To expand, add more elements to this array // and initialize them to zero (also initilaize them to zero at the start of the next test) - if(!P.FPGA) begin - updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); - end + updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); end //////////////////////////////////////////////////////////////////////////////// @@ -344,14 +342,14 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// always @(posedge clk) begin if (LoadMem) begin - if (P.FPGA) begin + if (P.SDC_SUPPORTED) begin string romfilename, sdcfilename; romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; - $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM); - $readmemh(sdcfilename, sdcard.sdcard.FLASHmem); + //$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM); + //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem); // shorten sdc timers for simulation - dut.uncore.uncore.sdc.SDC.LimitTimers = 1; + //dut.uncore.uncore.sdc.SDC.LimitTimers = 1; end else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); @@ -377,7 +375,7 @@ module testbench; assign {HRESPEXT, HRDATAEXT} = '0; end - if(P.FPGA) begin : sdcard + if(P.SDC_SUPPORTED) begin : sdcard // *** fix later /* -----\/----- EXCLUDED -----\/----- sdModel sdcard @@ -394,7 +392,7 @@ module testbench; assign SDCIntr = '0; end - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCIntr);