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Update fhazard.sv

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Program clean up
This commit is contained in:
Harshini Srinath 2023-06-11 16:06:44 -07:00 committed by GitHub
parent 610ac81a71
commit 4c4e6ca520
1 changed files with 0 additions and 3 deletions
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src/fpu/fhazard.sv
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@ -56,7 +56,6 @@ module fhazard(
// if the needed value is in the writeback stage // if the needed value is in the writeback stage
end else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FResult64W end else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FResult64W
// if the needed value is in the memory stage - input 2 // if the needed value is in the memory stage - input 2
if ((Adr2E == RdM) & FRegWriteM) begin if ((Adr2E == RdM) & FRegWriteM) begin
// if the result will be FResM (can be taken from the memory stage) // if the result will be FResM (can be taken from the memory stage)
@ -64,7 +63,6 @@ module fhazard(
// if the needed value is in the writeback stage // if the needed value is in the writeback stage
end else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FResult64W end else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FResult64W
// if the needed value is in the memory stage - input 3 // if the needed value is in the memory stage - input 3
if ((Adr3E == RdM) & FRegWriteM) begin if ((Adr3E == RdM) & FRegWriteM) begin
// if the result will be FResM (can be taken from the memory stage) // if the result will be FResM (can be taken from the memory stage)
@ -72,5 +70,4 @@ module fhazard(
// if the needed value is in the writeback stage // if the needed value is in the writeback stage
end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FResult64W end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FResult64W
end end
endmodule endmodule