From 4c4e6ca520c80d2ccde8729cc6a2addf07162127 Mon Sep 17 00:00:00 2001
From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com>
Date: Sun, 11 Jun 2023 16:06:44 -0700
Subject: [PATCH] Update fhazard.sv

Program clean up
---
 src/fpu/fhazard.sv | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/fpu/fhazard.sv b/src/fpu/fhazard.sv
index 0877abd9a..14f8c945f 100644
--- a/src/fpu/fhazard.sv
+++ b/src/fpu/fhazard.sv
@@ -56,7 +56,6 @@ module fhazard(
       // if the needed value is in the writeback stage
     end else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FResult64W
   
-
     // if the needed value is in the memory stage - input 2
     if ((Adr2E == RdM) & FRegWriteM) begin
       // if the result will be FResM (can be taken from the memory stage)
@@ -64,7 +63,6 @@ module fhazard(
       // if the needed value is in the writeback stage
     end else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FResult64W
 
-
     // if the needed value is in the memory stage - input 3
     if ((Adr3E == RdM) & FRegWriteM) begin
       // if the result will be FResM (can be taken from the memory stage)
@@ -72,5 +70,4 @@ module fhazard(
       // if the needed value is in the writeback stage
     end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FResult64W
   end 
-
 endmodule