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Cause simplification

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This commit is contained in:
David Harris 2022-05-12 23:47:21 +00:00
parent 9651ced9bb
commit 48e89485dd
4 changed files with 9 additions and 8 deletions
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6
pipelined/src/privileged/csr.sv
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@ -55,7 +55,7 @@ module csr #(parameter
input logic ICacheMiss, input logic ICacheMiss,
input logic ICacheAccess, input logic ICacheAccess,
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
input logic [`XLEN-1:0] CauseM, input logic [`LOG_XLEN-1:0] CauseM,
input logic SelHPTW, input logic SelHPTW,
output logic [1:0] STATUS_MPP, output logic [1:0] STATUS_MPP,
output logic STATUS_SPP, STATUS_TSR, STATUS_TVM, output logic STATUS_SPP, STATUS_TSR, STATUS_TVM,
@ -136,7 +136,7 @@ module csr #(parameter
if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec
always_comb always_comb
if (PrivilegedTrapVector[1:0] == 2'b01 & InterruptM) if (PrivilegedTrapVector[1:0] == 2'b01 & InterruptM)
PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + CauseM[`XLEN-3:0], 2'b00}; PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM}, 2'b00};
else else
PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
end end
@ -178,7 +178,7 @@ module csr #(parameter
assign CSRAdrM = InstrM[31:20]; assign CSRAdrM = InstrM[31:20];
assign UnalignedNextEPCM = TrapM ? ((wfiM & InterruptM) ? PCM+4 : PCM) : CSRWriteValM; assign UnalignedNextEPCM = TrapM ? ((wfiM & InterruptM) ? PCM+4 : PCM) : CSRWriteValM;
assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
assign NextCauseM = TrapM ? {InterruptM, CauseM[`XLEN-2:0]}: CSRWriteValM; assign NextCauseM = TrapM ? {InterruptM, {(`XLEN-`LOG_XLEN-1){1'b0}}, CauseM}: CSRWriteValM;
assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE); assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW); assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW);

2
pipelined/src/privileged/privileged.sv
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@ -81,7 +81,7 @@ module privileged (
output logic BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM output logic BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM
); );
logic [`XLEN-1:0] CauseM; logic [`LOG_XLEN-1:0] CauseM;
logic [`XLEN-1:0] MEDELEG_REGW; logic [`XLEN-1:0] MEDELEG_REGW;
logic [11:0] MIDELEG_REGW; logic [11:0] MIDELEG_REGW;

5
pipelined/src/privileged/privmode.sv
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@ -34,7 +34,8 @@
module privmode ( module privmode (
input logic clk, reset, input logic clk, reset,
input logic StallW, TrapM, mretM, sretM, InterruptM, input logic StallW, TrapM, mretM, sretM, InterruptM,
input logic [`XLEN-1:0] CauseM, MEDELEG_REGW, input logic [`LOG_XLEN-1:0] CauseM,
input logic [`XLEN-1:0] MEDELEG_REGW,
input logic [11:0] MIDELEG_REGW, input logic [11:0] MIDELEG_REGW,
input logic [1:0] STATUS_MPP, input logic [1:0] STATUS_MPP,
input logic STATUS_SPP, input logic STATUS_SPP,
@ -45,7 +46,7 @@ module privmode (
logic md; logic md;
// get bits of DELEG registers based on CAUSE // get bits of DELEG registers based on CAUSE
assign md = InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; assign md = InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM];
// PrivilegeMode FSM // PrivilegeMode FSM
always_comb begin always_comb begin

4
pipelined/src/privileged/trap.sv
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@ -44,7 +44,7 @@ module trap (
input logic InstrValidM, CommittedM, input logic InstrValidM, CommittedM,
output logic TrapM, RetM, output logic TrapM, RetM,
output logic InterruptM, IntPendingM, output logic InterruptM, IntPendingM,
output logic [`XLEN-1:0] CauseM output logic [`LOG_XLEN-1:0] CauseM
); );
logic MIntGlobalEnM, SIntGlobalEnM; logic MIntGlobalEnM, SIntGlobalEnM;
@ -94,7 +94,7 @@ module trap (
else if (IllegalInstrFaultM) CauseM = 2; else if (IllegalInstrFaultM) CauseM = 2;
else if (InstrMisalignedFaultM) CauseM = 0; else if (InstrMisalignedFaultM) CauseM = 0;
else if (BreakpointFaultM) CauseM = 3; else if (BreakpointFaultM) CauseM = 3;
else if (EcallFaultM) CauseM = {{(`XLEN-4){1'b0}}, {2'b10}, PrivilegeModeW}; else if (EcallFaultM) CauseM = {{(`LOG_XLEN-4){1'b0}}, {2'b10}, PrivilegeModeW};
else if (LoadMisalignedFaultM) CauseM = 4; else if (LoadMisalignedFaultM) CauseM = 4;
else if (StoreAmoMisalignedFaultM) CauseM = 6; else if (StoreAmoMisalignedFaultM) CauseM = 6;
else if (LoadPageFaultM) CauseM = 13; else if (LoadPageFaultM) CauseM = 13;