From 48e89485dda2456c6b735b94decf63805f997584 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 12 May 2022 23:47:21 +0000
Subject: [PATCH] Cause simplification

---
 pipelined/src/privileged/csr.sv        | 6 +++---
 pipelined/src/privileged/privileged.sv | 2 +-
 pipelined/src/privileged/privmode.sv   | 5 +++--
 pipelined/src/privileged/trap.sv       | 4 ++--
 4 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv
index fb78e8a99..23104f7fd 100644
--- a/pipelined/src/privileged/csr.sv
+++ b/pipelined/src/privileged/csr.sv
@@ -55,7 +55,7 @@ module csr #(parameter
   input  logic             ICacheMiss,
   input  logic             ICacheAccess,
   input  logic [1:0]       NextPrivilegeModeM, PrivilegeModeW,
-  input  logic [`XLEN-1:0] CauseM, 
+  input  logic [`LOG_XLEN-1:0] CauseM, 
   input  logic             SelHPTW,
   output logic [1:0]       STATUS_MPP,
   output logic             STATUS_SPP, STATUS_TSR, STATUS_TVM,
@@ -136,7 +136,7 @@ module csr #(parameter
   if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec
       always_comb
         if (PrivilegedTrapVector[1:0] == 2'b01 & InterruptM)
-          PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + CauseM[`XLEN-3:0], 2'b00};
+          PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM}, 2'b00};
         else
           PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
   end
@@ -178,7 +178,7 @@ module csr #(parameter
   assign CSRAdrM = InstrM[31:20];
   assign UnalignedNextEPCM = TrapM ? ((wfiM & InterruptM) ? PCM+4 : PCM) : CSRWriteValM;
   assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
-  assign NextCauseM = TrapM ? {InterruptM, CauseM[`XLEN-2:0]}: CSRWriteValM;
+  assign NextCauseM = TrapM ? {InterruptM, {(`XLEN-`LOG_XLEN-1){1'b0}}, CauseM}: CSRWriteValM;
   assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
   assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
   assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW);
diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv
index 8a5068a79..43e2f8f04 100644
--- a/pipelined/src/privileged/privileged.sv
+++ b/pipelined/src/privileged/privileged.sv
@@ -81,7 +81,7 @@ module privileged (
   output logic             BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM
 );
 
-  logic [`XLEN-1:0] CauseM;
+  logic [`LOG_XLEN-1:0] CauseM;
   logic [`XLEN-1:0] MEDELEG_REGW;
   logic [11:0]      MIDELEG_REGW;
 
diff --git a/pipelined/src/privileged/privmode.sv b/pipelined/src/privileged/privmode.sv
index 8fcd4905e..9446c08ce 100644
--- a/pipelined/src/privileged/privmode.sv
+++ b/pipelined/src/privileged/privmode.sv
@@ -34,7 +34,8 @@
 module privmode (
   input  logic             clk, reset,
   input  logic             StallW, TrapM, mretM, sretM, InterruptM,
-  input  logic [`XLEN-1:0] CauseM, MEDELEG_REGW,
+  input  logic [`LOG_XLEN-1:0] CauseM, 
+  input  logic [`XLEN-1:0] MEDELEG_REGW,
   input  logic [11:0]      MIDELEG_REGW,
   input  logic [1:0]       STATUS_MPP,
   input  logic             STATUS_SPP,
@@ -45,7 +46,7 @@ module privmode (
     logic       md;
 
     // get bits of DELEG registers based on CAUSE
-    assign md = InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]];
+    assign md = InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM];
     
     // PrivilegeMode FSM
     always_comb begin
diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv
index dffa73202..6225b9c05 100644
--- a/pipelined/src/privileged/trap.sv
+++ b/pipelined/src/privileged/trap.sv
@@ -44,7 +44,7 @@ module trap (
   input logic 		   InstrValidM, CommittedM, 
   output logic 		   TrapM, RetM,
   output logic 		   InterruptM, IntPendingM,
-  output logic [`XLEN-1:0] CauseM 
+  output logic [`LOG_XLEN-1:0] CauseM 
 );
 
   logic MIntGlobalEnM, SIntGlobalEnM;
@@ -94,7 +94,7 @@ module trap (
     else if (IllegalInstrFaultM)       CauseM = 2;
     else if (InstrMisalignedFaultM)    CauseM = 0;
     else if (BreakpointFaultM)         CauseM = 3;
-    else if (EcallFaultM)              CauseM = {{(`XLEN-4){1'b0}}, {2'b10}, PrivilegeModeW};
+    else if (EcallFaultM)              CauseM = {{(`LOG_XLEN-4){1'b0}}, {2'b10}, PrivilegeModeW};
     else if (LoadMisalignedFaultM)     CauseM = 4;
     else if (StoreAmoMisalignedFaultM) CauseM = 6;
     else if (LoadPageFaultM)           CauseM = 13;