Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Removed unnecessary display from testbench.

Browse Source
This commit is contained in:
Rose Thompson 2024-04-06 16:10:18 -05:00
parent 8885c32f7c
commit 46fdfde7ec
2 changed files with 6 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
sim/questa/sim-wally-batch
View File

@ -1 +1 @@
../wsim rv64gc arch64i wsim rv64gc arch64i

11
testbench/testbench.sv
View File

@ -108,8 +108,6 @@ module testbench;
TEST = "none"; TEST = "none";
if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT)) if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT))
INSTR_LIMIT = 0; INSTR_LIMIT = 0;
$display("INSTR_LIMIT = ", INSTR_LIMIT);
// pick tests based on modes supported // pick tests based on modes supported
//tests = '{}; //tests = '{};
@ -246,7 +244,7 @@ module testbench;
logic ResetCntRst; logic ResetCntRst;
logic CopyRAM; logic CopyRAM;
string signame, memfilename, bootmemfilename, uartoutfilename, pathname; string signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd;
integer begin_signature_addr, end_signature_addr, signature_size; integer begin_signature_addr, end_signature_addr, signature_size;
assign ResetThreshold = 3'd5; assign ResetThreshold = 3'd5;
@ -338,8 +336,9 @@ module testbench;
else if(TEST == "buildroot") begin else if(TEST == "buildroot") begin
memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"}; memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
uartoutfilename = {"logs/",TEST,"_uart.out"}; uartoutfilename = {"logs/", TEST, "_uart.out"};
$system("rm ",uartoutfilename); // Delete existing UARToutfile rmCmd = {"rm ", uartoutfilename};
$system(rmCmd); // Delete existing UARToutfile
end end
else memfilename = {pathname, tests[test], ".elf.memfile"}; else memfilename = {pathname, tests[test], ".elf.memfile"};
if (riscofTest) begin if (riscofTest) begin
@ -582,7 +581,7 @@ module testbench;
// Append UART output to file for tests // Append UART output to file for tests
always @(posedge clk) begin always @(posedge clk) begin
if (TEST == "buildroot") begin if (P.UART_SUPPORTED & TEST == "buildroot") begin
if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin
memFile = $fopen(uartoutfilename, "ab"); memFile = $fopen(uartoutfilename, "ab");
$fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din); $fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din);