From 46fdfde7ec98e1760901bd588cbd9557b7a13944 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Sat, 6 Apr 2024 16:10:18 -0500
Subject: [PATCH] Removed unnecessary display from testbench.

---
 sim/questa/sim-wally-batch |  2 +-
 testbench/testbench.sv     | 11 +++++------
 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/sim/questa/sim-wally-batch b/sim/questa/sim-wally-batch
index 58497efe9..7b3c69339 100755
--- a/sim/questa/sim-wally-batch
+++ b/sim/questa/sim-wally-batch
@@ -1 +1 @@
-../wsim rv64gc arch64i
+wsim rv64gc arch64i 
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 62f45691b..7145a2735 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -108,8 +108,6 @@ module testbench;
       TEST = "none";
     if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT))
       INSTR_LIMIT = 0;
-    $display("INSTR_LIMIT = ", INSTR_LIMIT);
-      
     
     // pick tests based on modes supported
     //tests = '{};
@@ -246,7 +244,7 @@ module testbench;
   logic        ResetCntRst;
   logic        CopyRAM;
 
-  string  signame, memfilename, bootmemfilename, uartoutfilename, pathname;
+  string  signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd;
   integer begin_signature_addr, end_signature_addr, signature_size;
 
   assign ResetThreshold = 3'd5;
@@ -338,8 +336,9 @@ module testbench;
       else if(TEST == "buildroot") begin 
         memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
         bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
-        uartoutfilename = {"logs/",TEST,"_uart.out"};
-        $system("rm ",uartoutfilename); // Delete existing UARToutfile
+        uartoutfilename = {"logs/", TEST, "_uart.out"};
+        rmCmd = {"rm ", uartoutfilename};
+        $system(rmCmd); // Delete existing UARToutfile
       end
       else            memfilename = {pathname, tests[test], ".elf.memfile"};
       if (riscofTest) begin
@@ -582,7 +581,7 @@ module testbench;
 
   // Append UART output to file for tests
   always @(posedge clk) begin
-    if (TEST == "buildroot") begin
+    if (P.UART_SUPPORTED & TEST == "buildroot") begin
       if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin
         memFile = $fopen(uartoutfilename, "ab");
         $fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din);