diff --git a/bin/CModelBTBAccuracy.sh b/bin/CModelBTBAccuracy.sh index 479340eb2..20a65bf98 100755 --- a/bin/CModelBTBAccuracy.sh +++ b/bin/CModelBTBAccuracy.sh @@ -9,6 +9,7 @@ ## Computes the geometric mean for btb accuracy ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/CModelBranchAccuracy.sh b/bin/CModelBranchAccuracy.sh index 8253891bb..2fb7b164a 100755 --- a/bin/CModelBranchAccuracy.sh +++ b/bin/CModelBranchAccuracy.sh @@ -9,6 +9,7 @@ ## Computes the geometric mean. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/CacheSim.py b/bin/CacheSim.py index 24857837b..f6b2cb7e1 100755 --- a/bin/CacheSim.py +++ b/bin/CacheSim.py @@ -10,6 +10,7 @@ ## Purpose: Simulate a L1 D$ or I$ for comparison with Wally ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/SeparateBranch.sh b/bin/SeparateBranch.sh index c81ba32c9..87648589f 100755 --- a/bin/SeparateBranch.sh +++ b/bin/SeparateBranch.sh @@ -12,6 +12,7 @@ ## separated by benchmark application. Example names are aha-mot64bd_sizeopt_speed_branch.log ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/derivgen.pl b/bin/derivgen.pl new file mode 100644 index 000000000..fcb6f8179 --- /dev/null +++ b/bin/derivgen.pl @@ -0,0 +1,58 @@ +#!/bin/perl -W + +########################################### +## derivgen.pl +## +## Written: David_Harris@hmc.edu +## Created: 29 January 2024 +## Modified: +## +## Purpose: Read config/derivlist.txt and generate config/deriv/*/config.vh +## derivative configurations from the base configurations +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw +## https://github.com/openhwgroup/cvw +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + + +use strict; +use warnings; +import os; + +if ($#ARGV != 0) { + die("Usage: $0 workpath [e.g. $0 \$WALLY/addins/riscv-arch-test/work") +} +my $mypath = $ARGV[0]; +my @dirs = glob($mypath.'/*/*'); +foreach my $dir (@dirs) { + $dir =~ /.*\/(.*)\/(.*)/; + my $arch = $1; + my $ext = $2; + my $contents = `grep --with-filename ":" $dir/*.objdump`; + my @lines = split('\n', $contents); + print "$arch/$ext"; + foreach my $line (@lines) { + $line =~ /.*\/(.*)\.elf.objdump:(\S*)/; + my $fname = $1; + my $adr = $2; + my $partialaddress = substr($adr, -6); + print ",\n\t\t\"$arch/$ext/$fname\", \"$partialaddress\""; + } + print("\n\n"); +} diff --git a/bin/elf2hex.sh b/bin/elf2hex.sh index 56f286135..d36678e9c 100755 --- a/bin/elf2hex.sh +++ b/bin/elf2hex.sh @@ -9,6 +9,7 @@ ## Imperas and riscv-arch-test benchmarks ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/exe2memfile.pl b/bin/exe2memfile.pl index 2af665bbd..4f04ff512 100755 --- a/bin/exe2memfile.pl +++ b/bin/exe2memfile.pl @@ -11,6 +11,7 @@ ## to read into a Verilog simulation with $readmemh ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/fparchtest.sh b/bin/fparchtest.sh new file mode 100755 index 000000000..7ea690e96 --- /dev/null +++ b/bin/fparchtest.sh @@ -0,0 +1,21 @@ +#!/usr/bin/bash +# +# fparchtest.sh +# David_Harris@hmc.edu 26 December 2023 +# +# Drive the riscv-isac and riscv-ctg tools to generate floating-point tests + +# Set up with (not retested) +# cd ~/repos +# git clone https://github.com/riscv/riscv-ctg.git +# git clone https://github.com/riscv/riscv-isac.git +# pip3 install git+https://github.com/riscv/riscv-ctg.git +# pip3 install git+https://github.com/riscv/riscv-isac.git +# Put ~/.local/bin in $PATH to find riscv_isac and riscv_ctg + +RISCVCTG=/home/harris/repos/riscv-ctg + +#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf -o $RISCVCTG/tests/normalizedfadd.cgf -x 32 +#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32H/fadd_b1.s.cgf -o $RISCVCTG/tests/normalizedfadd16_b1.cgf -x 32 +riscv_ctg -cf $RISCVCTG/tests/normalizedfadd16_b1.cgf -d $RISCVCTG/tests --base-isa rv32i --verbose debug +#riscv_ctg -cf $RISCVCTG/sample_cgfs/dataset.cgf -cf $RISCVCTG/sample_cgfs/rv32im.cgf -d $RISCVCTG/tests --base-isa rv32i # --verbose debug diff --git a/bin/imperas-one-time.sh b/bin/imperas-one-time.sh index 404636d7c..339b4c74f 100755 --- a/bin/imperas-one-time.sh +++ b/bin/imperas-one-time.sh @@ -9,6 +9,7 @@ ## Purpose: One time setup script for running imperas. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/libppa.pl b/bin/libppa.pl index ccf4f1548..9f1e8515d 100755 --- a/bin/libppa.pl +++ b/bin/libppa.pl @@ -13,6 +13,7 @@ ## and for TSMC change the $cellname to the actual name of the inverter. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 7e8eb7cde..73535c430 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -8,6 +8,7 @@ ## Purpose: Parses the performance counters from a modelsim trace. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/testcount.pl b/bin/testcount.pl index e801ed0e4..139902dd3 100755 --- a/bin/testcount.pl +++ b/bin/testcount.pl @@ -12,6 +12,7 @@ ## and count how many tests are in each ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/testlist.pl b/bin/testlist.pl index 655cdd6f8..c72b96961 100755 --- a/bin/testlist.pl +++ b/bin/testlist.pl @@ -11,6 +11,7 @@ ## and generate a list of tests and signature addresses for tests.vh ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/vclean.pl b/bin/vclean.pl index f947ed9d0..294d1d435 100755 --- a/bin/vclean.pl +++ b/bin/vclean.pl @@ -11,6 +11,7 @@ ## verilator should do this, but it also reports partially used signals ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 7ccb1a138..6e7e4c8e9 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -10,6 +10,7 @@ ## Purpose: Open source tool chain installation script ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/config/derivlist.txt b/config/derivlist.txt new file mode 100644 index 000000000..554697e62 --- /dev/null +++ b/config/derivlist.txt @@ -0,0 +1,73 @@ +########################################### +## derivlist.txt +## Wally Derivative Configuration List +## +## Written: David_Harris@hmc.edu +## Created: 29 January 2024 +## Modified: +## +## Purpose: Used by sim/make deriv to generate derivative configurations +## in config/deriv that are variants of the base configurations. +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + +# Format: +# begin a derivative with "deriv +# Followed by a list of parameters and their new value in the derivative configuration +# All other parameter values are inherited from the original configuration +# If is not empty, all the list of parameter changes in the inherited +# configuration are also applied to this configuration + +deriv buildroot rv64gc +RESET_VECTOR 64'h1000 +UNCORE_RAM_RANGE 64'h0FFFFFFF +UNCORE_RAM_PRELOAD 1 +GPIO_LOOPBACK_TEST 0 +SPI_LOOBACK_TEST 0 +UART_PRESCALE 0 +PLIC_NUM_SRC 32'd53 + +deriv fpga rv64gc buildroot +BOOTROM_PRELOAD 1 +UNCORE_RAM_BASE 64'h2000 +UNCORE_RAM_RANGE 64'hFFF +EXT_MEM_SUPPORTED 1 +EXT_MEM_BASE 64'h80000000 +EXT_MEM_RANGE 64'h0FFFFFFF +SDC_SUPPORTED 1 +PLIC_SDC_ID 32'd20 +BPRED_SIZE 32'd12 + +deriv syn_rv32e rv32e +DTIM_RANGE 32'h1FF +IROM_RANGE 32'h1FF +BOOTROM_RANGE 32'h1FF +UNCORE_RAM_RANGE 32'h1FF +BOOTROM_RANGE 32'h1FF +WAYSIZEINBYTES 32'd512 +NUMWAYS 32'd1 +BPRED_SIZE 32'd5 +BTB_SIZE 32'd5 + +deriv syn_rv32i rv32i syn_rv32e +deriv syn_rv32imc rv32imc syn_rv32e +deriv syn_rv32gc rv32gc syn_rv32e +deriv syn_rv64i rv64i syn_rv32e +deriv syn_rv64gc rv64gc syn_rv32e diff --git a/docs/Dockerfile b/docs/Dockerfile index b06f9ad67..8df933363 100755 --- a/docs/Dockerfile +++ b/docs/Dockerfile @@ -7,6 +7,7 @@ ## Purpose: Dockerfile for Wally docker container creation ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/generator/insert_debug_comment.sh b/fpga/generator/insert_debug_comment.sh index 66c232e16..35fa05a02 100755 --- a/fpga/generator/insert_debug_comment.sh +++ b/fpga/generator/insert_debug_comment.sh @@ -7,6 +7,7 @@ ## Modified: 20 January 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/probe b/fpga/probe index 21e5d8240..1cf1104c1 100755 --- a/fpga/probe +++ b/fpga/probe @@ -7,6 +7,7 @@ ## Modified: 16 August 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/proberange b/fpga/proberange index 715cba46e..73bfc3383 100755 --- a/fpga/proberange +++ b/fpga/proberange @@ -7,6 +7,7 @@ ## Modified: 16 August 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/fpga/probes b/fpga/probes index 83c2ddf7c..1ea571057 100755 --- a/fpga/probes +++ b/fpga/probes @@ -7,6 +7,7 @@ ## Modified: 16 August 2023 ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/gitflow.txt b/gitflow.txt index 57300830a..f6f70de74 100644 --- a/gitflow.txt +++ b/gitflow.txt @@ -1,5 +1,6 @@ ########################################### ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index e39128f5a..b6eb0214f 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -7,6 +7,7 @@ #// For example, signals hardwired to 0 should not be checked for toggle coverage #// #// A component of the CORE-V-WALLY configurable RISC-V project. +#// https://github.com/openhwgroup/cvw #// #// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University #// diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py index 42f21c8c6..bc75fc13a 100755 --- a/sim/rv64gc_CacheSim.py +++ b/sim/rv64gc_CacheSim.py @@ -10,6 +10,7 @@ ## Purpose: Run the cache simulator on each rv64gc test suite in turn. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/sim/sim-imperas b/sim/sim-imperas index aa1dc3a01..556cdebf6 100755 --- a/sim/sim-imperas +++ b/sim/sim-imperas @@ -10,6 +10,7 @@ ## Purpose: Run wally with imperas ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 86aba57a0..4a97a29d4 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.10, and 7.19) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index b593f2ae6..70f129d4b 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.15 to 7.18) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 07494c2a9..0d3b2c0e0 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 9c5523cec..b2be76838 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index db80cfc83..95920ec7e 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 7 // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index 5f2dff313..89135966e 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.8) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index df84175f0..8852b52c3 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.21) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index 8d434c678..e9dadb515 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv index 81d11715e..e49a6313a 100644 --- a/src/ebu/busfsm.sv +++ b/src/ebu/busfsm.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.23) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv index 60df9e44b..67e4795a6 100644 --- a/src/ebu/controllerinput.sv +++ b/src/ebu/controllerinput.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.25) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 4a1b00b57..d9a95fc3d 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 302c4752f..55ba9a506 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fclassify.sv b/src/fpu/fclassify.sv index bfc7a53dd..f35f71869 100644 --- a/src/fpu/fclassify.sv +++ b/src/fpu/fclassify.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fcmp.sv b/src/fpu/fcmp.sv index 227676203..0944090fc 100755 --- a/src/fpu/fcmp.sv +++ b/src/fpu/fcmp.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 705a112d1..60edbfd8a 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index a4e20f229..85a1a5494 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv index 1e6eda56c..2649632eb 100644 --- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv +++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index bbb2d9360..d24b490ab 100644 --- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv index cf398f570..bc9dce536 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index e2cec1ab4..a04523e58 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index cd890ed87..f7d21e5d8 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv index 863d94837..20f88b6cb 100644 --- a/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 5a40a3bdc..c3954bc0a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 939b9c133..1c56e04e5 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv index 40a2a5a01..c3d6e210c 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv index a24c1155f..0d7a722ff 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv index c895fa2ce..032bb700e 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv index b12b9174b..19e322013 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv index e4fcfeadf..2d4cd5e48 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv index b44b34a35..63ea5aae2 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv index ccb5e618a..c0cbe9b1c 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fhazard.sv b/src/fpu/fhazard.sv index 14f8c945f..e68934294 100644 --- a/src/fpu/fhazard.sv +++ b/src/fpu/fhazard.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fli.sv b/src/fpu/fli.sv index e61415388..dedb230b0 100644 --- a/src/fpu/fli.sv +++ b/src/fpu/fli.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 16 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fma.sv b/src/fpu/fma/fma.sv index a6e87a240..321bfe8bc 100644 --- a/src/fpu/fma/fma.sv +++ b/src/fpu/fma/fma.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.7, 9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv index 98ff21491..1ad3b0b83 100644 --- a/src/fpu/fma/fmaadd.sv +++ b/src/fpu/fma/fmaadd.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv index efc4a4c5f..9001742e4 100644 --- a/src/fpu/fma/fmaalign.sv +++ b/src/fpu/fma/fmaalign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmaexpadd.sv b/src/fpu/fma/fmaexpadd.sv index bb7bf2437..06ac7e290 100644 --- a/src/fpu/fma/fmaexpadd.sv +++ b/src/fpu/fma/fmaexpadd.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv index 66659665a..822f857c2 100644 --- a/src/fpu/fma/fmalza.sv +++ b/src/fpu/fma/fmalza.sv @@ -10,6 +10,7 @@ // See also [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001] // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmamult.sv b/src/fpu/fma/fmamult.sv index 91f255b87..8ce492f03 100644 --- a/src/fpu/fma/fmamult.sv +++ b/src/fpu/fma/fmamult.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fma/fmasign.sv b/src/fpu/fma/fmasign.sv index aca6c8f8c..2a8b827d2 100644 --- a/src/fpu/fma/fmasign.sv +++ b/src/fpu/fma/fmasign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.8) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 05d5f2e00..90ec10dee 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv index 6ab14df20..2de41088b 100644 --- a/src/fpu/fregfile.sv +++ b/src/fpu/fregfile.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv index cee13f4f9..4fe03522b 100755 --- a/src/fpu/fsgninj.sv +++ b/src/fpu/fsgninj.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv index 77b8543fd..d3ce45f2e 100644 --- a/src/fpu/postproc/cvtshiftcalc.sv +++ b/src/fpu/postproc/cvtshiftcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv index 9e5de7173..0a222d724 100644 --- a/src/fpu/postproc/divshiftcalc.sv +++ b/src/fpu/postproc/divshiftcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv index 40fe887ca..21160e0c5 100644 --- a/src/fpu/postproc/flags.sv +++ b/src/fpu/postproc/flags.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv index b13b6d3da..e16f51615 100644 --- a/src/fpu/postproc/fmashiftcalc.sv +++ b/src/fpu/postproc/fmashiftcalc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/negateintres.sv b/src/fpu/postproc/negateintres.sv index d0aaf760b..5ca848b0b 100644 --- a/src/fpu/postproc/negateintres.sv +++ b/src/fpu/postproc/negateintres.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/normshift.sv b/src/fpu/postproc/normshift.sv index f24a75fe1..f235d4d5b 100644 --- a/src/fpu/postproc/normshift.sv +++ b/src/fpu/postproc/normshift.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv index 1d51fdf85..e30058538 100644 --- a/src/fpu/postproc/postprocess.sv +++ b/src/fpu/postproc/postprocess.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv index 0dd22c1f4..2d5587dcf 100644 --- a/src/fpu/postproc/resultsign.sv +++ b/src/fpu/postproc/resultsign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv index 445f563d9..aae3d68f4 100644 --- a/src/fpu/postproc/round.sv +++ b/src/fpu/postproc/round.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/roundsign.sv b/src/fpu/postproc/roundsign.sv index 6c1135602..521675ac4 100644 --- a/src/fpu/postproc/roundsign.sv +++ b/src/fpu/postproc/roundsign.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv index f5860b42d..275ee4cff 100644 --- a/src/fpu/postproc/shiftcorrection.sv +++ b/src/fpu/postproc/shiftcorrection.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv index ba30daaf2..0a787c27c 100644 --- a/src/fpu/postproc/specialcase.sv +++ b/src/fpu/postproc/specialcase.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv index 145d6a701..eab224dd9 100644 --- a/src/fpu/unpack.sv +++ b/src/fpu/unpack.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index b3d7f901e..ca58c9d9f 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 13 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/adder.sv b/src/generic/adder.sv index 4d341d6c1..f499eca88 100644 --- a/src/generic/adder.sv +++ b/src/generic/adder.sv @@ -7,6 +7,7 @@ // Purpose: Adder // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv index f8d675b33..dc5f6450c 100644 --- a/src/generic/aplusbeq0.sv +++ b/src/generic/aplusbeq0.sv @@ -7,6 +7,7 @@ // Purpose: Determine if A+B = 0. Used in FP divider. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/arrs.sv b/src/generic/arrs.sv index dd473b307..cbff0e82b 100644 --- a/src/generic/arrs.sv +++ b/src/generic/arrs.sv @@ -10,6 +10,7 @@ // rising edge, but then syncs the falling edge to the posedge clk. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/binencoder.sv b/src/generic/binencoder.sv index 89093ea5b..a9349879a 100644 --- a/src/generic/binencoder.sv +++ b/src/generic/binencoder.sv @@ -6,6 +6,7 @@ // Purpose: one-hot to binary encoding. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/clockgater.sv b/src/generic/clockgater.sv index c0150133c..48282ccfa 100644 --- a/src/generic/clockgater.sv +++ b/src/generic/clockgater.sv @@ -7,6 +7,7 @@ // Purpose: Clock gater model. Must use standard cell for synthesis. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/counter.sv b/src/generic/counter.sv index faba2e5e5..cc20ae71e 100644 --- a/src/generic/counter.sv +++ b/src/generic/counter.sv @@ -7,6 +7,7 @@ // Purpose: Counter with reset and enable // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/csa.sv b/src/generic/csa.sv index 91aef44dd..ac9dfe098 100644 --- a/src/generic/csa.sv +++ b/src/generic/csa.sv @@ -7,6 +7,7 @@ // Purpose: 3:2 carry-save adder // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/decoder.sv b/src/generic/decoder.sv index 6284a454c..78b816c3c 100644 --- a/src/generic/decoder.sv +++ b/src/generic/decoder.sv @@ -7,6 +7,7 @@ // Purpose: Binary encoding to one-hot decoder // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flop.sv b/src/generic/flop/flop.sv index 97e0ac7e4..b7e7a82ee 100644 --- a/src/generic/flop/flop.sv +++ b/src/generic/flop/flop.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopen.sv b/src/generic/flop/flopen.sv index 2e6432519..f1db84776 100644 --- a/src/generic/flop/flopen.sv +++ b/src/generic/flop/flopen.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopenl.sv b/src/generic/flop/flopenl.sv index 562c4565a..08b6590a8 100644 --- a/src/generic/flop/flopenl.sv +++ b/src/generic/flop/flopenl.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable and synchronous load // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv index 2c2144ab8..565fbfa7a 100644 --- a/src/generic/flop/flopenr.sv +++ b/src/generic/flop/flopenr.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable, synchronous reset // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv index 94b2b3cb0..983fae5f2 100644 --- a/src/generic/flop/flopenrc.sv +++ b/src/generic/flop/flopenrc.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable, synchronous reset, enabled clear // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv index c4fc5d01b..11c128393 100644 --- a/src/generic/flop/flopens.sv +++ b/src/generic/flop/flopens.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with enable, synchronous set // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv index 2e39ee8d6..b3edcbdf9 100644 --- a/src/generic/flop/flopr.sv +++ b/src/generic/flop/flopr.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with synchronous reset // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/floprc.sv b/src/generic/flop/floprc.sv index b35e9ccce..59f2e2862 100644 --- a/src/generic/flop/floprc.sv +++ b/src/generic/flop/floprc.sv @@ -7,6 +7,7 @@ // Purpose: D flip-flop with synchronous reset and clear // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/flop/synchronizer.sv b/src/generic/flop/synchronizer.sv index f99088af4..d4a63cd53 100644 --- a/src/generic/flop/synchronizer.sv +++ b/src/generic/flop/synchronizer.sv @@ -7,6 +7,7 @@ // Purpose: Two-stage flip-flop synchronizer // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/lzc.sv b/src/generic/lzc.sv index aa5381a22..855b64d88 100644 --- a/src/generic/lzc.sv +++ b/src/generic/lzc.sv @@ -6,6 +6,7 @@ // Purpose: Leading Zero Counter // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 4af3c255c..ccfce5da2 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -13,6 +13,7 @@ // Documentation: // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv index 55b1d75b0..64ddec259 100755 --- a/src/generic/mem/ram1p1rwbe_64x128.sv +++ b/src/generic/mem/ram1p1rwbe_64x128.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwbe_64x22.sv b/src/generic/mem/ram1p1rwbe_64x22.sv index 5e7a4c5cf..1b5e1bdb7 100755 --- a/src/generic/mem/ram1p1rwbe_64x22.sv +++ b/src/generic/mem/ram1p1rwbe_64x22.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv index a2c2c81fa..1744ba59f 100644 --- a/src/generic/mem/ram1p1rwbe_64x44.sv +++ b/src/generic/mem/ram1p1rwbe_64x44.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index e3746c181..ebe7e336b 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -11,6 +11,7 @@ // Documentation: // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 42435c607..0945684d3 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -12,6 +12,7 @@ // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_1024x36.sv b/src/generic/mem/ram2p1r1wbe_1024x36.sv index 302277ed0..d499442b4 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x36.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x36.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv index 6da7e06d6..a1633f8e9 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x68.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_128x64.sv b/src/generic/mem/ram2p1r1wbe_128x64.sv index e181fdd07..54d0ee8dc 100644 --- a/src/generic/mem/ram2p1r1wbe_128x64.sv +++ b/src/generic/mem/ram2p1r1wbe_128x64.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_512x64.sv b/src/generic/mem/ram2p1r1wbe_512x64.sv index 442eff90d..95185346a 100644 --- a/src/generic/mem/ram2p1r1wbe_512x64.sv +++ b/src/generic/mem/ram2p1r1wbe_512x64.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv index 4236bb3f6..db3cbc846 100755 --- a/src/generic/mem/ram2p1r1wbe_64x32.sv +++ b/src/generic/mem/ram2p1r1wbe_64x32.sv @@ -7,6 +7,7 @@ // Purpose: RAM wrapper for instantiating RAM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index c298dba63..cc94f1b96 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -6,6 +6,7 @@ // Purpose: Single-ported ROM // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/rom1p1r_128x32.sv b/src/generic/mem/rom1p1r_128x32.sv index ea5b92054..0854f1557 100755 --- a/src/generic/mem/rom1p1r_128x32.sv +++ b/src/generic/mem/rom1p1r_128x32.sv @@ -7,6 +7,7 @@ // Purpose: ROM wrapper for instantiating ROM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mem/rom1p1r_128x64.sv b/src/generic/mem/rom1p1r_128x64.sv index 6712d10fa..7a86bc50e 100755 --- a/src/generic/mem/rom1p1r_128x64.sv +++ b/src/generic/mem/rom1p1r_128x64.sv @@ -7,6 +7,7 @@ // Purpose: ROM wrapper for instantiating ROM IP // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/mux.sv b/src/generic/mux.sv index 9c1dfe335..5a4767c87 100644 --- a/src/generic/mux.sv +++ b/src/generic/mux.sv @@ -7,6 +7,7 @@ // Purpose: Various flavors of multiplexers // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/neg.sv b/src/generic/neg.sv index e971fc232..8621e510e 100644 --- a/src/generic/neg.sv +++ b/src/generic/neg.sv @@ -7,6 +7,7 @@ // Purpose: 2's complement negator // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv index b672a08e5..9b25feb65 100644 --- a/src/generic/onehotdecoder.sv +++ b/src/generic/onehotdecoder.sv @@ -7,6 +7,7 @@ // Purpose: Bin to one hot decoder. Power of 2 only. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/or_rows.sv b/src/generic/or_rows.sv index 476b62586..56e693abb 100644 --- a/src/generic/or_rows.sv +++ b/src/generic/or_rows.sv @@ -7,6 +7,7 @@ // Purpose: Perform OR across a 2-dimensional array of inputs to produce a 1-D array of outputs // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/priorityonehot.sv b/src/generic/priorityonehot.sv index 1cddb2bfc..65882dd75 100644 --- a/src/generic/priorityonehot.sv +++ b/src/generic/priorityonehot.sv @@ -17,6 +17,7 @@ // out 00000000000100000 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/generic/prioritythermometer.sv b/src/generic/prioritythermometer.sv index f779d4748..23acfcfb3 100644 --- a/src/generic/prioritythermometer.sv +++ b/src/generic/prioritythermometer.sv @@ -13,6 +13,7 @@ // out 00000000000011111 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 3728ceb17..140c3e74e 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4, Figure 13.54 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 4c296fda2..51cf00b97 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 4a5b4bfab..3f7d0ae7a 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index fc2530aab..3876c31e4 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 59a8e4a16..5b758f123 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/byteop.sv b/src/ieu/bmu/byteop.sv index 2879ba042..191919ecc 100644 --- a/src/ieu/bmu/byteop.sv +++ b/src/ieu/bmu/byteop.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 675387577..f32fcece9 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index d015c1195..eb54d6e3c 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 1feca6e1e..5ce1139fb 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 7701c0d65..903b67eeb 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 9ae3df42d..52ed8ef34 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 4dc3ad1bd..6e1948c33 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/comparator.sv b/src/ieu/comparator.sv index 0803d8b2f..466167fb3 100644 --- a/src/ieu/comparator.sv +++ b/src/ieu/comparator.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index e5cfff9ed..b18df36ec 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index c2bcaf8c3..eb6fd1d81 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/extend.sv b/src/ieu/extend.sv index 4f7ee387f..b090c3f5e 100644 --- a/src/ieu/extend.sv +++ b/src/ieu/extend.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.3) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 870a37963..5a2b8d6dc 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv index 2b76bca17..bf6990ea9 100644 --- a/src/ieu/regfile.sv +++ b/src/ieu/regfile.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index bb0160c71..af44b6136 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index bc245d984..9f5dd2a43 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 64297c44a..faf537d91 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -9,6 +9,7 @@ // Prediction made during the fetch stage and corrected in the execution stage. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 567e4d3cd..2d0d30727 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index fcdf46655..7f5906084 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -10,6 +10,7 @@ // Purpose: gshare and Global History Branch predictors // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index 7ae9f0282..1fa6f21f6 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -10,6 +10,7 @@ // Purpose: Global History Branch predictor with parameterized global history register // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv index e4895d4b7..42bde6f4e 100644 --- a/src/ifu/bpred/icpred.sv +++ b/src/ifu/bpred/icpred.sv @@ -9,6 +9,7 @@ // Call, Return, Jump, and Branch // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv index 4d6d536a7..fd8acbc82 100644 --- a/src/ifu/bpred/localaheadbp.sv +++ b/src/ifu/bpred/localaheadbp.sv @@ -8,6 +8,7 @@ // Purpose: local history branch predictor with ahead pipelining and SRAM memories. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv index d3a694c33..5c4485f3f 100644 --- a/src/ifu/bpred/localbpbasic.sv +++ b/src/ifu/bpred/localbpbasic.sv @@ -9,6 +9,7 @@ // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index 95399e65a..3a730bd41 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -8,6 +8,7 @@ // Purpose: Local history branch predictor with speculation and repair using CBH. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/satCounter2.sv b/src/ifu/bpred/satCounter2.sv index 470375adc..7dd33ffb3 100644 --- a/src/ifu/bpred/satCounter2.sv +++ b/src/ifu/bpred/satCounter2.sv @@ -9,6 +9,7 @@ // Purpose: 2 bit starting counter // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv index 5b2fcb9b8..583b8d805 100644 --- a/src/ifu/bpred/twoBitPredictor.sv +++ b/src/ifu/bpred/twoBitPredictor.sv @@ -9,6 +9,7 @@ // Purpose: 2 bit saturating counter predictor with parameterized table depth. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 50617d3c5..e6c4fcd9a 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -12,6 +12,7 @@ // *** probably need more documentation in this file since the book is very light on decompression. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 0bd899306..be2595ea6 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -8,6 +8,7 @@ // PC, branch prediction, instruction cache // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/irom.sv b/src/ifu/irom.sv index 0b29c72cf..e5e7a7f96 100644 --- a/src/ifu/irom.sv +++ b/src/ifu/irom.sv @@ -7,6 +7,7 @@ // // Purpose: simple instruction ROM // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index 39b30abd1..ea045c43f 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/align.sv b/src/lsu/align.sv index 8710b1d6a..d516dad2a 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv index c8b7ccee3..4d6330215 100644 --- a/src/lsu/amoalu.sv +++ b/src/lsu/amoalu.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 117a42c2b..7dbd0c8a2 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index a44086a15..1386db96f 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/endianswap.sv b/src/lsu/endianswap.sv index 551f08de4..7c042886a 100644 --- a/src/lsu/endianswap.sv +++ b/src/lsu/endianswap.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv index 66a9956dc..f7d1d4799 100644 --- a/src/lsu/lrsc.sv +++ b/src/lsu/lrsc.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 220a42eef..ca4e14f53 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.2) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/subwordread.sv b/src/lsu/subwordread.sv index e5666eb84..82fb80fb1 100644 --- a/src/lsu/subwordread.sv +++ b/src/lsu/subwordread.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/subwordwrite.sv b/src/lsu/subwordwrite.sv index ad21b3c25..705672ff7 100644 --- a/src/lsu/subwordwrite.sv +++ b/src/lsu/subwordwrite.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv index 5737bdc9b..60164e081 100644 --- a/src/lsu/swbytemask.sv +++ b/src/lsu/swbytemask.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mdu/div.sv b/src/mdu/div.sv index c550c06fc..2ae35d8f4 100644 --- a/src/mdu/div.sv +++ b/src/mdu/div.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mdu/divstep.sv b/src/mdu/divstep.sv index 712e98866..f478ad86f 100644 --- a/src/mdu/divstep.sv +++ b/src/mdu/divstep.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv index e152fc6de..886eaf2b3 100644 --- a/src/mdu/mdu.sv +++ b/src/mdu/mdu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.21) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mdu/mul.sv b/src/mdu/mul.sv index a5946b95c..65eaefd82 100644 --- a/src/mdu/mul.sv +++ b/src/mdu/mul.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.18) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/adrdec.sv b/src/mmu/adrdec.sv index 492d55372..05ac45bd0 100644 --- a/src/mmu/adrdec.sv +++ b/src/mmu/adrdec.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv index 282918484..d71fef82a 100644 --- a/src/mmu/adrdecs.sv +++ b/src/mmu/adrdecs.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 2a99b14fd..0823dc7e0 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -13,6 +13,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index 6957ed315..e842016a2 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv index 896274554..84e41ba65 100644 --- a/src/mmu/pmachecker.sv +++ b/src/mmu/pmachecker.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index 9f283772d..7226237f6 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -13,6 +13,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index 97cc6a18d..30a525744 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv index a417bb530..5fbd10caf 100644 --- a/src/mmu/tlb/tlb.sv +++ b/src/mmu/tlb/tlb.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbcam.sv b/src/mmu/tlb/tlbcam.sv index e591498c4..aa569f2dd 100644 --- a/src/mmu/tlb/tlbcam.sv +++ b/src/mmu/tlb/tlbcam.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbcamline.sv b/src/mmu/tlb/tlbcamline.sv index 9471fb3d9..f5856ef56 100644 --- a/src/mmu/tlb/tlbcamline.sv +++ b/src/mmu/tlb/tlbcamline.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv index aa9ec348a..83074deb3 100644 --- a/src/mmu/tlb/tlbcontrol.sv +++ b/src/mmu/tlb/tlbcontrol.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlblru.sv b/src/mmu/tlb/tlblru.sv index 18014155a..4776b5afb 100644 --- a/src/mmu/tlb/tlblru.sv +++ b/src/mmu/tlb/tlblru.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbmixer.sv b/src/mmu/tlb/tlbmixer.sv index 9652e21ef..4a8712da9 100644 --- a/src/mmu/tlb/tlbmixer.sv +++ b/src/mmu/tlb/tlbmixer.sv @@ -12,6 +12,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbram.sv b/src/mmu/tlb/tlbram.sv index 1a667d847..620f338a1 100644 --- a/src/mmu/tlb/tlbram.sv +++ b/src/mmu/tlb/tlbram.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/tlbramline.sv b/src/mmu/tlb/tlbramline.sv index 5e17e86eb..910db3aec 100644 --- a/src/mmu/tlb/tlbramline.sv +++ b/src/mmu/tlb/tlbramline.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/mmu/tlb/vm64check.sv b/src/mmu/tlb/vm64check.sv index a089031c2..4a4e96387 100644 --- a/src/mmu/tlb/vm64check.sv +++ b/src/mmu/tlb/vm64check.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 8 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index e43712d81..e4dda5121 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index c3dbf1f6b..348ba1596 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -11,6 +11,7 @@ // MHPMEVENT is not supported // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv index ea7bf7afb..35b6f3fe6 100644 --- a/src/privileged/csri.sv +++ b/src/privileged/csri.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 056e8f2f9..9f5b29428 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index e107fc0f7..2357fc131 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 9935da179..3a28c5075 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/csru.sv b/src/privileged/csru.sv index 3a0f8c909..37891d009 100644 --- a/src/privileged/csru.sv +++ b/src/privileged/csru.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index a5bfde1cf..bc9f9235f 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 2d217b6d6..d6ef8d9d1 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.8) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/privmode.sv b/src/privileged/privmode.sv index 5ac4cae78..f1c5bfd76 100644 --- a/src/privileged/privmode.sv +++ b/src/privileged/privmode.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/privpiperegs.sv b/src/privileged/privpiperegs.sv index 5dea45972..ed43571bd 100644 --- a/src/privileged/privpiperegs.sv +++ b/src/privileged/privpiperegs.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index 43ff8eadc..f20604379 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv index 454f4d5df..dc7ceeab3 100644 --- a/src/uncore/ahbapbbridge.sv +++ b/src/uncore/ahbapbbridge.sv @@ -8,6 +8,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv index 6e35ffdaf..691ba372d 100644 --- a/src/uncore/clint_apb.sv +++ b/src/uncore/clint_apb.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv index 4ba3e1ccf..3b4ae1cb0 100644 --- a/src/uncore/gpio_apb.sv +++ b/src/uncore/gpio_apb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 8ced27319..4c0602353 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -14,6 +14,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 896c2a4cb..0b15504c9 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv index d94cd6e07..9576f33d7 100644 --- a/src/uncore/rom_ahb.sv +++ b/src/uncore/rom_ahb.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design Chapter 6 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index ad1e0f259..f8aa4e016 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -16,6 +16,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv index 6fab04189..eeecb7ea5 100644 --- a/src/uncore/uart_apb.sv +++ b/src/uncore/uart_apb.sv @@ -11,6 +11,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 1675d5a38..22e0a35fc 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 15 (and Figure 6.20) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 79c4364cb..c0d08dd8c 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design (Figure 4.1) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index ab0071fff..d82a5c0d4 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -9,6 +9,7 @@ // Documentation: RISC-V System on Chip Design (Figure 6.20) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/studies/comparator.sv b/studies/comparator.sv index a5dbb6cb6..01d38181b 100644 --- a/studies/comparator.sv +++ b/studies/comparator.sv @@ -10,6 +10,7 @@ // Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/synthDC/extractArea.pl b/synthDC/extractArea.pl index 5f595dad8..fa630a3e7 100755 --- a/synthDC/extractArea.pl +++ b/synthDC/extractArea.pl @@ -10,6 +10,7 @@ ## Purpose: Pull area statistics from run directory ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ## diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index fdf9be6cf..edf867240 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -6,6 +6,7 @@ // Purpose: Initialize stack, handle interrupts, terminate test case // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S index ce5639bd7..3fe499abd 100644 --- a/tests/coverage/csrwrites.S +++ b/tests/coverage/csrwrites.S @@ -6,6 +6,7 @@ // Purpose: Test writes to CSRs // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/dcache2.S b/tests/coverage/dcache2.S index 58f97a2e4..7d5905288 100644 --- a/tests/coverage/dcache2.S +++ b/tests/coverage/dcache2.S @@ -7,6 +7,7 @@ // (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1) // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/ebu.S b/tests/coverage/ebu.S index c6be8e4ef..fa7927d95 100644 --- a/tests/coverage/ebu.S +++ b/tests/coverage/ebu.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for EBU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 0e3fd80d7..ca68e7275 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for FPU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/ieu.S b/tests/coverage/ieu.S index 1e32a24ab..7ec318632 100644 --- a/tests/coverage/ieu.S +++ b/tests/coverage/ieu.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for IEU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S index 0866326cc..4b085d845 100644 --- a/tests/coverage/ifu.S +++ b/tests/coverage/ifu.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for IFU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/ifuCamlineWrite.S b/tests/coverage/ifuCamlineWrite.S index 4c11bf183..db873dec4 100644 --- a/tests/coverage/ifuCamlineWrite.S +++ b/tests/coverage/ifuCamlineWrite.S @@ -9,6 +9,7 @@ // Purpose: Test coverage for TLBCamlines in IFU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/lsu.S b/tests/coverage/lsu.S index 9ccb32aa8..0e065010e 100644 --- a/tests/coverage/lsu.S +++ b/tests/coverage/lsu.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for lsu // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 39b3a8aeb..105a61e11 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for EBU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbASID.S b/tests/coverage/tlbASID.S index 278568147..ecf66feed 100644 --- a/tests/coverage/tlbASID.S +++ b/tests/coverage/tlbASID.S @@ -7,6 +7,7 @@ // Purpose: Test coverage for LSU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbGLB.S b/tests/coverage/tlbGLB.S index e6ae534bd..de1541610 100644 --- a/tests/coverage/tlbGLB.S +++ b/tests/coverage/tlbGLB.S @@ -8,6 +8,7 @@ // Purpose: Coverage for the Page Table Entry Global flag check. // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbGP.S b/tests/coverage/tlbGP.S index ede79f13e..bbdb703b4 100644 --- a/tests/coverage/tlbGP.S +++ b/tests/coverage/tlbGP.S @@ -7,6 +7,7 @@ // Purpose: Create Page tables and access gigapages // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbKP.S b/tests/coverage/tlbKP.S index 5aaf5c195..4382673ea 100644 --- a/tests/coverage/tlbKP.S +++ b/tests/coverage/tlbKP.S @@ -7,6 +7,7 @@ // Purpose: Test coverage for LSU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbM3.S b/tests/coverage/tlbM3.S index ececa1f34..eba37ae99 100644 --- a/tests/coverage/tlbM3.S +++ b/tests/coverage/tlbM3.S @@ -7,6 +7,7 @@ // Purpose: Test coverage for LSU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbMP.S b/tests/coverage/tlbMP.S index 043e5dc4a..f6dc4c597 100644 --- a/tests/coverage/tlbMP.S +++ b/tests/coverage/tlbMP.S @@ -7,6 +7,7 @@ // Purpose: Test coverage for LSU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbNAPOT.S b/tests/coverage/tlbNAPOT.S index 15af7ea30..56d2943f4 100644 --- a/tests/coverage/tlbNAPOT.S +++ b/tests/coverage/tlbNAPOT.S @@ -8,6 +8,7 @@ // Purpose: Test coverage for LSU NAPOT // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbTP.S b/tests/coverage/tlbTP.S index 54857afbd..f4b0a142e 100644 --- a/tests/coverage/tlbTP.S +++ b/tests/coverage/tlbTP.S @@ -7,6 +7,7 @@ // Purpose: Test coverage for LSU // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S index eeb1c7d34..4bbb4958a 100644 --- a/tests/coverage/tlbmisc.S +++ b/tests/coverage/tlbmisc.S @@ -6,6 +6,7 @@ // Purpose: Test coverage for other TLB issues // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/coverage/vm64check.S b/tests/coverage/vm64check.S index 55c4db959..2e03a4e1a 100644 --- a/tests/coverage/vm64check.S +++ b/tests/coverage/vm64check.S @@ -6,6 +6,7 @@ // Purpose: vm64check coverage // // A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/tests/custom/cacheSimTest/CacheSimTest.py b/tests/custom/cacheSimTest/CacheSimTest.py index 44cc00b06..e81b87d55 100755 --- a/tests/custom/cacheSimTest/CacheSimTest.py +++ b/tests/custom/cacheSimTest/CacheSimTest.py @@ -10,6 +10,7 @@ ## Purpose: Confirm that the cache simulator behaves as expected. ## ## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw ## ## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University ##