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Comments for dcache and icache refactoring.

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This commit is contained in:
Ross Thompson 2021-12-14 14:46:29 -06:00
parent ee5c2e6101
commit 45b38ea9fe
2 changed files with 14 additions and 1 deletions
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5
wally-pipelined/src/ifu/ifu.sv
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@ -115,6 +115,7 @@ module ifu (
endgenerate endgenerate
assign PCFExt = {2'b00, PCF}; assign PCFExt = {2'b00, PCF};
//
mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1)) mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
immu(.PAdr(PCFExt[`PA_BITS-1:0]), immu(.PAdr(PCFExt[`PA_BITS-1:0]),
.VAdr(PCF), .VAdr(PCF),
@ -158,6 +159,10 @@ module ifu (
//assign InstrReadF = ~StallD; // *** & ICacheMissF; add later //assign InstrReadF = ~StallD; // *** & ICacheMissF; add later
// assign InstrReadF = 1; // *** & ICacheMissF; add later // assign InstrReadF = 1; // *** & ICacheMissF; add later
// conditional
// 1. dtim // controlled by `MEM_IROM
// 2. cache // `MEM_ICACHE
// 3. wire pass-through
icache icache(.clk, .reset, .StallF, .ExceptionM, .PendingInterruptM, .InstrInF, .InstrAckF, icache icache(.clk, .reset, .StallF, .ExceptionM, .PendingInterruptM, .InstrInF, .InstrAckF,
.InstrPAdrF, .InstrReadF, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF, .InstrPAdrF, .InstrReadF, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF,

8
wally-pipelined/src/lsu/lsu.sv
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@ -129,6 +129,8 @@ module lsu
assign AnyCPUReqM = (|MemRWM) | (|AtomicM); assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
// *** add generate to conditionally create hptw, lsuArb, and mmu
// based on `MEM_VIRTMEM
hptw hptw(.clk(clk), hptw hptw(.clk(clk),
.reset(reset), .reset(reset),
.SATP_REGW(SATP_REGW), .SATP_REGW(SATP_REGW),
@ -210,6 +212,7 @@ module lsu
); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist? ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
// Move generate from lrsc to outside this module.
assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
lrsc lrsc(.clk, .reset, .FlushW, .StallWtoDCache, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM, lrsc lrsc(.clk, .reset, .FlushW, .StallWtoDCache, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM,
.SquashSCW, .MemRWMtoDCache); .SquashSCW, .MemRWMtoDCache);
@ -219,6 +222,7 @@ module lsu
// Specify which type of page fault is occurring // Specify which type of page fault is occurring
// *** `MEM_VIRTMEM
assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoLRSC[1]; assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoLRSC[1];
assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoLRSC[0]; assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoLRSC[0];
@ -235,6 +239,10 @@ module lsu
assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[1]; assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[1];
assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[0]; assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[0];
// conditional
// 1. dtim // controlled by `MEM_DTIM
// 2. cache `MEM_DCACHE
// 3. wire pass-through
dcache dcache(.clk(clk), dcache dcache(.clk(clk),
.reset(reset), .reset(reset),
.StallWtoDCache(StallWtoDCache), .StallWtoDCache(StallWtoDCache),