From 45b38ea9fe2c2133f03ad2b88f932d17da087d22 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 14 Dec 2021 14:46:29 -0600
Subject: [PATCH] Comments for dcache and icache refactoring.

---
 wally-pipelined/src/ifu/ifu.sv |  5 +++++
 wally-pipelined/src/lsu/lsu.sv | 10 +++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index c0bfaaf80..b54553529 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -115,6 +115,7 @@ module ifu (
   endgenerate
 
   assign PCFExt = {2'b00, PCF};
+  //
   mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
   immu(.PAdr(PCFExt[`PA_BITS-1:0]),
        .VAdr(PCF),
@@ -158,6 +159,10 @@ module ifu (
   //assign InstrReadF = ~StallD; // *** & ICacheMissF; add later
   // assign InstrReadF = 1; // *** & ICacheMissF; add later
 
+  // conditional
+  // 1. dtim // controlled by `MEM_IROM
+  // 2. cache // `MEM_ICACHE
+  // 3. wire pass-through
   icache icache(.clk, .reset, .StallF, .ExceptionM, .PendingInterruptM, .InstrInF, .InstrAckF,
   .InstrPAdrF, .InstrReadF, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF,
 
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 75ae4ccd3..01fcb7334 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -128,7 +128,9 @@ module lsu
   logic 		       MemAfterIWalkDone;
 
   assign AnyCPUReqM = (|MemRWM)  | (|AtomicM);
-  
+
+  // *** add generate to conditionally create hptw, lsuArb, and mmu
+  // based on `MEM_VIRTMEM
   hptw hptw(.clk(clk),
 	    .reset(reset),
 	    .SATP_REGW(SATP_REGW),
@@ -210,6 +212,7 @@ module lsu
        ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
 
 
+  // Move generate from lrsc to outside this module.
   assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
   lrsc lrsc(.clk, .reset, .FlushW, .StallWtoDCache, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM,
             .SquashSCW, .MemRWMtoDCache);
@@ -219,6 +222,7 @@ module lsu
   
 
   // Specify which type of page fault is occurring
+  // *** `MEM_VIRTMEM
   assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoLRSC[1];
   assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoLRSC[0];
 
@@ -235,6 +239,10 @@ module lsu
   assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[1];
   assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[0];
 
+  // conditional
+  // 1. dtim // controlled by `MEM_DTIM
+  // 2. cache `MEM_DCACHE
+  // 3. wire pass-through
   dcache dcache(.clk(clk),
 		.reset(reset),
 		.StallWtoDCache(StallWtoDCache),